Synchronous digital signal phase detection method and circuit based on FPGA

Abstract

The invention relates to the technical field of digital signal receiving, in particular to a synchronous digital signal phase detection method and circuit based on an FPGA, and the method comprises the steps: outputting two paths of same-frequency clocks for clock phase locking of the synchronous digital signal, using two paths of same-frequency clocks respectively latching an input digital signal, and calculating a latched result, obtaining a intermediate result, outputting and metering the intermediate result so as to judge the phase of the digital signal relative to the clock; and a logic circuit which consists of a clock manager, a common trigger, a gate circuit and the like. The invention provides a novel digital signal phase detection method, which solves the risk of unreliability of blind clock phase sampling signals, the problem that only low-frequency signals can be detected is solved; detection of internal signals of the printed circuit board is realized; the common-frequency method is provided, the requirement for the time sequence speed of an FPGA device is lowered, common logic circuits of the FPGA are adopted, and the common-frequency method is simple and has universality.

Description

technical field [0001] The invention relates to the technical field of digital signal reception, in particular to an FPGA-based synchronous digital signal phase detection method and circuit. Background technique [0002] In the past synchronous data link transmission, in order to analyze the line transmission situation, an oscilloscope is usually used to measure the clock and data signals at the same time, and by observing the position of the signal jump, the timing problem can be accurately analyzed. However, many current hardware design signal lines are placed in the For the inner layer of the printed circuit board, the oscilloscope can only capture the surface layer signal, but cannot analyze the inner layer signal. Or by sampling the synchronous clock in the link at a high frequency, like the principle of an oscilloscope, to achieve multi-rate sampling of the signal, and to observe the jump position of the digital signal, you can determine the jump phase of the synchroni...

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Problems solved by technology

[0002] In the past synchronous data link transmission, in order to analyze the line transmission situation, an oscilloscope is usually used to measure the clock and data signals at the same time, and by observing the position of the signal jump, the timing problem can be accurately analyzed. However, many current hardware design signal lines are placed in the On the inner layer of the printed circuit board, the oscilloscope can only capture the surface layer signal, but cannot analyze the inner layer signal

Or by sampling the synchronous clock in the link at a high frequency, like the principle of an oscilloscope, to achieve multi-rate sampling of the signal, and to observe the jump position of the digital signal, you can determine the jump phase of the synchronization signal, but this method is only applicable Because the signal change speed is much lower than the working frequency of the FPGA device, because the device operating frequency is limited, the signal frequency that can be detected is very low. Therefore, in the case of high signal frequency, the common method in engineering practice is multiple trial and error. , by adjusting the sampling clock phase of the synchronous signal, comparing the sampling result with the expected expected result, and then repeatedly experimenting to obtain an empirical value, but this method does not find the root of the problem, but only solves the problem of sampling error from the surface phenomenon

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