A FPGA-based synchronous digital signal phase detection method and circuit

Abstract

The present invention relates to the technical field of digital signal reception, in particular to an FPGA-based synchronous digital signal phase detection method and circuit, which includes phase-locking the clock of the synchronous digital signal and outputting two channels of same-frequency clocks, and using the two channels of same-frequency clocks to unlock respectively Store the input digital signal, and operate on the latched result to obtain an intermediate result, sample and output the intermediate result and measure it to judge the phase of the digital signal relative to the clock; and include a clock manager and common trigger Logic circuits composed of devices, gate circuits, etc. The invention provides a new method for detecting the phase of a digital signal, which solves the risk of unreliable sampling signals of the blindly adjusted clock phase; solves the problem that only low-frequency signals can be detected; realizes the detection of the internal signal of the printed circuit board; provides A co-frequency method is proposed, which reduces the requirement on the timing speed of FPGA devices, and uses common logic circuits of FPGA, which is simple and versatile.

Description

technical field [0001] The invention relates to the technical field of digital signal reception, in particular to an FPGA-based synchronous digital signal phase detection method and circuit. Background technique [0002] In the past synchronous data link transmission, in order to analyze the line transmission situation, an oscilloscope is usually used to measure the clock and data signals at the same time, and by observing the position of the signal jump, the timing problem can be accurately analyzed. However, many current hardware design signal lines are placed in the For the inner layer of the printed circuit board, the oscilloscope can only capture the surface layer signal, but cannot analyze the inner layer signal. Or by sampling the synchronous clock in the link at a high frequency, like the principle of an oscilloscope, to achieve multi-rate sampling of the signal, and to observe the jump position of the digital signal, you can determine the jump phase of the synchroni...

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Problems solved by technology

[0002] In the past synchronous data link transmission, in order to analyze the line transmission situation, an oscilloscope is usually used to measure the clock and data signals at the same time, and by observing the position of the signal jump, the timing problem can be accurately analyzed. However, many current hardware design signal lines are placed in the On the inner layer of the printed circuit board, the oscilloscope can only capture the surface layer signal, but cannot analyze the inner layer signal

Or by sampling the synchronous clock in the link at a high frequency, like the principle of an oscilloscope, to achieve multi-rate sampling of the signal, and to observe the jump position of the digital signal, you can determine the jump phase of the synchronization signal, but this method is only applicable Because the signal change speed is much lower than the working frequency of the FPGA device, because the device operating frequency is limited, the signal frequency that can be detected is very low. Therefore, in the case of high signal frequency, the common method in engineering practice is multiple trial and error. , by adjusting the sampling clock phase of the synchronous signal, comparing the sampling result with the expected expected result, and then repeatedly experimenting to obtain an empirical value, but this method does not find the root of the problem, but only solves the problem of sampling error from the surface phenomenon

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