Test fixture and test device

Abstract

The invention discloses a test fixture, which comprises a first connection fixture, an extension board, and a second connection fixture. The first connection fixture is provided with a first male connector connected with a hard disk interface to be tested and a PCIE signal transmitter. The extension board is provided with a PCIE signal input end, an internal wire and a PCIE signal output end, the PCIE signal input end is connected with the PCIE signal transmitter to receive a PCIE signal, and the PCIE signal is output through the PCIE signal output end after being transmitted through the internal wire. The second connection fixture is provided with a PCIE signal receiver and a female connector, the PCIE signal receiver is connected with the PCIE signal output end to receive a PCIE signal, the PCIE signal is output through the female connector, and then the PCIE signal extended by the extension board is tested. The invention further provides a test device. According to the test fixture provided by the embodiment of the invention, the first connection fixture is connected to the position of a hard disk interface on a back plane and then is switched to the extension board, and the loss after signal extension is tested in combination with the design of the second connection fixture.

Description

technical field [0001] The invention relates to the field of testing, in particular to a testing fixture and a testing device. Background technique [0002] In order to improve product competitiveness and achieve low cost and high reliability of a storage product, it is necessary to thoroughly understand the capability limit of the chip storage interface to ensure that the signal travels a longer distance under low-cost PCB materials while meeting the signal integrity requirements. In order to ensure that the actual work does not produce bit errors. At present, the U.2 interface is a common interface for PCIE SSD hard disks, and has been widely used in various products. At present, there are two main methods to evaluate the signal quality risk of the interface. One is to evaluate the signal risk through simulation modeling. However, because engineering manufacturing tolerances and modeling cannot fully fit the reality, people usually build similar environments based on exis...

AI Technical Summary

Problems solved by technology

However, due to the diversity of combinations of interconnection interfaces between the mainboard and the backplane, there are often situations where existing products cannot build similar links, and the scope of application of this method is limited.

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