Parallel pipelined decompression device for FPGA configuration code stream

A pipelined, decompression technology, applied in the field of communication, to achieve the effect of improving device parallelism, simplifying implementation complexity, and decompressing efficiently

Active Publication Date: 2021-12-03
北京中科胜芯科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The technical problem to be solved by the present invention is: how to shorten the configuration time and improve the configuration efficiency in the case of a huge amount of configuration data, and simplify the implementation complexity of the LZ77 algorithm while ensuring the same performance as the LZ77 algorithm. data structure

Method used

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  • Parallel pipelined decompression device for FPGA configuration code stream
  • Parallel pipelined decompression device for FPGA configuration code stream
  • Parallel pipelined decompression device for FPGA configuration code stream

Examples

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Embodiment 1

[0019] This embodiment is a parallel pipeline decompression device for FPGA configuration code stream, such as figure 1 , as shown, including a state generator and some parallel structures; the state generator is connected with each parallel structure, and the parallel structure receives the compressed data for configuring the FPGA;

[0020] The state generator is used to control the configuration code stream data through the chip selection enabling control mode for the compressed data; send state information, including idle state, receiving packet header state, decompression state, and completion state; The controller of the device sends system information, and the system information includes counting information in the state of receiving the packet header, counting information in the decompressed state, and chip selection control information for configuring the compressed code stream;

[0021] The parallel structure includes a configuration code stream parser, a shift regist...

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Abstract

The invention relates to a parallel pipelined decompression device for FPGA (Field Programmable Gate Array) configuration code streams, and belongs to the technical field of communication. The device comprises a state generator and a plurality of parallel structural bodies, the state generator is connected with each parallel structural body, and the parallel structural bodies are used for receiving compressed data used for configuring the FPGA; each parallel structural body comprises a configuration code stream analyzer, a shift register and a decompression unit, and forms a processing structure in a three-level assembly line mode. The parallel structure body mode is adopted, the parallelism degree of the device is flexibly improved, and the decompression efficiency is improved; a three-level assembly line mode is adopted, the decompression time is shortened to one third compared with a serial mode, and decompression is more efficient.

Description

technical field [0001] The invention relates to a parallel pipeline type decompression device for FPGA configuration code stream, which belongs to the technical field of communication. Background technique [0002] As the scale of FPGA chip logic resources becomes larger and larger, the amount of configuration data is huge, and the transmission time in the configuration process becomes a bottleneck. Improving transmission bandwidth, shortening configuration time, and improving configuration efficiency have become critical and sensitive. Contents of the invention [0003] The technical problem to be solved by the present invention is: how to shorten the configuration time and improve the configuration efficiency in the case of a huge amount of configuration data, and simplify the implementation complexity of the LZ77 algorithm while ensuring the same performance as the LZ77 algorithm. The way the data is structured. (The LZ77 algorithm uses an adaptive dictionary model, i....

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M7/30
CPCH03M7/3086Y02D10/00
Inventor 王佳薇舒毅
Owner 北京中科胜芯科技有限公司
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