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A method to reduce chip power consumption

A power consumption and chip technology, applied in the field of reducing chip power consumption, can solve the problem of unrealistic chip power off, and achieve the effect of reducing chip power consumption

Active Publication Date: 2022-07-05
ANHUI DONGKE SEMICON CO LTD
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  • Abstract
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Problems solved by technology

[0003] However, for a working chip, it is obviously unrealistic to power down the entire chip

Method used

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  • A method to reduce chip power consumption
  • A method to reduce chip power consumption

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Embodiment Construction

[0022] The present invention will be further described below through the accompanying drawings and specific embodiments, but it should be understood that these embodiments are only used for more detailed description, and should not be construed as limiting the present invention in any form, that is, it is not intended to to limit the protection scope of the present invention.

[0023] The embodiment of the present invention provides a method for reducing chip power consumption, and the main process is as follows figure 1 shown, including the following steps:

[0024] Step 110, determine the power consumption demand of the power consumption load in the chip module;

[0025] Specifically, the electrical load includes a standard cell (STD cell) and a hard macro (Hard Macro) in the chip module; the electrical demand of the electrical load refers to the power supply requirement of the electrical load when the circuit module is working normally.

[0026] Step 120: Determine a plur...

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Abstract

The present invention relates to a method for reducing power consumption of a chip, comprising: determining the power demand of an electrical load in a chip module; the electrical load includes standard cells and hard macros in the chip module; according to the physical location of the electrical load, determining a plurality of Turn-off domains; wherein, each turn-off domain contains one or more standard cells and / or one or more hard macros; according to the positions of hard macros and standard cells in the turn-off domain, in the turn-off domain Correspondingly insert the switch unit in the switch unit; establish a first stacking hole between the high-level power supply network and the switch unit, and establish a second stacking hole between the switch unit and the transition layer power supply network; the switch unit is connected according to the received control signal or Disconnect standard cells and hard macros from the power supply.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a method for reducing chip power consumption. Background technique [0002] In the field of low-power design, the most effective way to reduce power consumption is to turn off the power supply. The reason is that no matter how low the voltage, how small the current, how slow the speed or how small the leakage, it is better to turn off the power completely. [0003] However, for a working chip, it is obviously unrealistic to power down the entire chip. Then, if the modules that do not work in the chip can be turned off, and the modules that keep working continue to work, real low power consumption can be achieved. [0004] In the existing chip, the power network is realized through layers of metal, the top metal is always maintained in a power-on state, and the bottom metal is connected to the top metal through layers of holes for power transmission. [0005] ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/3287G06F1/3296
CPCG06F1/3287G06F1/3296Y02D10/00
Inventor 赵少峰
Owner ANHUI DONGKE SEMICON CO LTD
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