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Memory cell array of programmable non-volatile memory

A storage unit array and storage unit technology, applied in static memory, read-only memory, digital memory information, etc., can solve the problem of large size

Active Publication Date: 2021-12-17
EMEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is to say, the existing programmable and erasable non-volatile memory will include N-type well region (NW) and P-type well region (PW), resulting in the size of the existing programmable and erasable non-volatile memory (size) larger

Method used

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  • Memory cell array of programmable non-volatile memory
  • Memory cell array of programmable non-volatile memory
  • Memory cell array of programmable non-volatile memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0037] Figures 2A to 2E Production process programmable non-volatile memory of the present invention. According to an embodiment of the present invention, non-volatile memory can be programmed once (OTP) non-volatile memory, erasable or repeatedly programming (MTP) non-volatile memory. Further, in this production process, a memory cell is described the production process, but the present invention is not limited thereto.

[0038] First of all, if Figure 2A Shown, an N-type well region (N-well region, NW) on a semiconductor substrate (substrate). Wherein the semiconductor substrate may be a p-type semiconductor substrate (p-substrate).

[0039] Next, the isolation structure (isolation structure) forming step. like Figure 2b , In the semiconductor substrate (not shown), N-type well region NW surfaces defining a width D of a rectangular area 210. Subsequently, an outer rectangular region 210 in the isolation structure 205 is formed, to retain only the surface of the N-type well regi...

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PUM

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Abstract

The invention discloses a memory cell array of a programmable non-volatile memory. A memory cell in the memory cell array comprises a well region, a first doped region, a second doped region, a first gate structure and a memory structure. The first doped region and the second doped region are formed in the well region. The first gate structure covers a first surface between the first doped region and the second doped region. The storage structure is formed on a second surface, and the second surface is located between the first surface and the second doped region. The storage structure covers a part of the first gate structure, the second surface and an isolation structure.

Description

Technical field [0001] The present invention relates to a memory cell array of a non-volatile memory (non-volatile memory), and in particular relates to a memory cell array is a programmable non-volatile memory. Background technique [0002] Please refer to Figures 1A to 1C , A storage unit (memory cell) which is a conventional erasable programmable non-volatile memory. The erasable programmable non-volatile memory of a memory cell disclosed in U.S. Patent No. US8,941,167. [0003] Figure 1A Is a top view of the conventional non-volatile memory; Figure 1B A first direction prior to non-volatile memory (a1-a2 direction) cross-sectional view; Figure 1C A second direction cross-sectional view of the conventional non-volatile memory (b1-b2 direction). [0004] Depend on Figure 1A and Figure 1B Understood, conventional non-volatile memory storage unit included in two serially connected p-type transistor fabricated on an N-type well region (NW). 32, 33 includes, three upper surface of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/1157H01L27/11575H01L27/11578
CPCH10B43/50H10B43/20H10B43/35G11C16/10G11C16/14G11C16/26G11C16/3409G11C16/0433G11C2216/10H01L29/42328H10B41/10H10B41/30G11C11/1675G11C13/0038G11C11/1697G11C13/0069G11C16/08G11C16/24G11C16/30H10B41/35
Inventor 许家荣孙文堂
Owner EMEMORY TECH INC
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