Memristor-based programmable neural network accelerator

Abstract

The invention belongs to the field of novel intelligent computing processors, and relates to a memristor-based programmable neural network accelerator which is connected in series with an SOC bus through an interface and comprises an instruction processing module, a control unit and an execution unit module. The control unit is in control connection with the instruction processing module and the execution unit module, the instruction processing module is formed by sequentially connecting an instruction memory, an instruction fetching unit and an instruction decoding unit into a whole, transmits instruction information to the control unit after performing access decoding on an instruction, and transmits data on the instruction to the execution unit module; the execution unit module comprises an arithmetic logic unit, a vector processing unit, a data memory and a memristor storage unit; the arithmetic logic unit and the vector processing unit are respectively and correspondingly responsible for register calculation and vector calculation; and the data memory is connected with the memristor storage unit and then is connected with the vector processing unit. The accelerator has the advantages of high flexibility, low bandwidth requirement, low power consumption and high degree of parallelism.

Description

technical field [0001] The invention belongs to the field of novel intelligent computing processors, and relates to a memristor-based programmable neural network accelerator. Background technique [0002] With the large-scale application of artificial intelligence, AI chips have gradually become popular. Compared with traditional processing chips, AI chips have higher computing power and energy efficiency. Most of the current AI chips for deep learning network acceleration are mainly optimized for parallel computing to improve the performance of their chips, such as IBM's TrueNorth, Google's TPU, and Cambrian's DIANNAO. However, as the network scale and data scale increase, the bandwidth and energy consumption required by the traditional von Neumann architecture AI chip are increasing, and the "memory wall" problem caused by its architecture has become increasingly prominent. Therefore, both academia and industry are constantly exploring a new architecture system and techn...

AI Technical Summary

Problems solved by technology

However, with the increase of network scale and data scale, the bandwidth and energy consumption required by traditional von Neumann architecture AI chips are increasing, and the problem of "memory wall" caused by its architecture has become increasingly prominent.

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