Wallace tree compressor based on Xilinx FPGA primitive

Abstract

The invention provides a Wallace tree compressor based on a Xilinx FPGA primitive. The Wallace tree compressor is composed of a tree type compression structure and a final summation unit. The tree-shaped compression structure compresses a plurality of binary numbers to two or three outputs, and the summing module adds compression results and outputs a final result. The tree-shaped compression structure takes a 4: 2 compressor as a basic compression unit and is matched with a 3: 2 compressor when necessary. The bit level structure of the 4: 2 compressor comprises an LUT6-2 module, a first muxcy module and a first xorcy module which are used for original intonation of the Xilinx FPGA; the LUT6-2 module is configured to be two LUT5 which share input and independently output, and two independent binary functions can be realized; and the first muxcy module and the first xorcy module are special carry logic resources in the CLB and are configured into a 3: 2 compressor. A 3: 1 compressor is designed as a final summation unit of the Wallace tree according to the same thought. The method is used for achieving multi-operand addition and subtraction operation, the utilization rate of hardware resources is greatly improved, and the overall delay and power consumption of the Wallace tree are reduced.

Description

technical field [0001] The invention belongs to the technical field of application of programmable logic chips, in particular to a Wallace tree compressor based on Xilinx FPGA primitives. Background technique [0002] Wallace tree is a multi-stage compression structure composed of a series of compressors, which can quickly complete multi-operand addition and subtraction operations, and is widely used in parallel hardware multiplication, vector point multiplication and other operations. In the earliest proposal proposed by Wallace himself, a tree-type compression structure was built with a Carry Save Adder (CSA) with a compression ratio of 3:2 as the basic module. Dadda has since proposed a new type of compression unit called a "j-k counter". In practical applications, the 5-3 counter (that is, the 4:2 compressor) has become the most widely used compression unit in multipliers due to its better balance and symmetry, and higher compression efficiency than CSA. [0003] When ...

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Problems solved by technology

[0007] However, under the influence of FPGA synthesizer, the above two 4:2 compressors have the same resource consumption and similar critical path delay despite different implementation methods

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