A production process of chip resistors loaded on ceramic substrates
A technology of ceramic substrates and chip resistors, which is applied in the direction of resistors, resistors, and resistors at the lead-out end, so as to avoid excessive tearing and complete rupture.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
specific Embodiment 1
[0070] Specific embodiment one: a kind of chip resistor production process loaded on the ceramic substrate, comprises the following steps:
[0071] a. A ceramic substrate 1 is provided. Both the upper end surface and the lower end surface of the ceramic substrate 1 are provided with a plurality of transverse folding lines and a plurality of longitudinal folding lines. The folding line and the folding block line cross each other to form a plurality of grid areas. The position of the fold line on the lower end face corresponds to the position of the fold line on the upper end face one by one. The grid area on the upper end face corresponds to the grid area on the lower end face one by one. The position of the fold line on the lower end surface corresponds to the position of the fold line on the upper end face one by one. A groove 101 is defined between every two adjacent folding lines on the upper end surface of the ceramic substrate 1 .
[0072] b. Print the silver-palladiu...
specific Embodiment 2
[0086] Specific embodiment two: on the basis of specific embodiment one, please refer to Figure 1-11 A production process of a chip resistor loaded on a ceramic substrate, comprising the following steps:
[0087] a. A ceramic substrate 1 is provided. Both the upper end surface and the lower end surface of the ceramic substrate 1 are provided with a plurality of transverse folding lines and a plurality of longitudinal folding lines. The folding line and the folding block line cross each other to form a plurality of grid areas. The position of the fold line on the lower end face corresponds to the position of the fold line on the upper end face one by one. The grid area on the upper end face corresponds to the grid area on the lower end face one by one. The position of the fold line on the lower end surface corresponds to the position of the fold line on the upper end face one by one. A groove 101 is defined between every two adjacent folding lines on the upper end surface ...
specific Embodiment 3
[0094] Specific embodiment three: On the basis of specific embodiment two, a chip resistor production process loaded on a ceramic substrate, the opening width of the groove 101 is from one front electrode 2 close to the other front electrode 2 end to the other One front electrode 2 , that is, the area between two front electrodes 2 is covered by the groove 101 . This effectively avoids the problem that the torn part of the second resistive layer 5 cannot be in contact with the first resistive layer 4 because the tearing position of the second resistive layer 5 is too close to the front electrode 2 .
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


