Multi-level cache security

Abstract

In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The CPU is arranged to execute program instructions (1000) to manipulate data in at least a first or second secure context. Each of the first and second caches stores (e.g., 1050) a secure code for indicating the at least first or second secure contexts by which data for a respective cache line is received. The first and second level caches maintain coherency in response to comparing (1020) the secure codes of respective lines of cache and executing (1030) a cache coherency operation in response.

Description

Background technique [0001] The processing device may be formed as part of an integrated circuit, such as part of a system on chip (SoC). In some examples, the SoC includes at least one central processing unit (CPU), where each CPU of the SoC is coupled to an integrated (eg, shared) memory system. The memory system may include, for example, multi-level cache memory (e.g., static RAM—SRAM—formed on an integrated circuit of the SoC) and at least one main memory (e.g., dynamic RAM—DRAM and / or DDR—which may be integrated on the SoC. memory outside the circuit). [0002] Increasingly complex memory architectures continue to provide scalability challenges when more and more powerful CPUs are added (or coupled) to processing devices. When multiple CPUs share a common address space of a memory system, scalability challenges still exist and can become even greater. Portions of the common address space of the shared memory may include various levels of a coherent cache (eg, where eac...

AI Technical Summary

Problems solved by technology

Such delays can be extended when the cache is configured to protect certain areas of the cache memory from being read or altered by at least one CPU that would otherwise be allowed to access the line of the cache

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