Dynamic power consumption test device and method for programmable logic device

Abstract

The invention discloses a dynamic power consumption test method and device for a programmable logic device. The device comprises a clock generation unit, a winding resource excitation unit, a winding resource test unit and a current sampling unit which are connected in sequence. The clock generation unit is used for generating a periodically flipping clock signal and transmitting the clock signal to the winding resource excitation unit, the winding resource test unit is used for generating different dynamic power consumption, and the dynamic power consumption value is calculated by sampling an output driving current of a power supply of a programmable logic device and a preset voltage. Dynamic power consumption values in respective modes are measured by testing different winding resource interconnection modes, and the dynamic power consumption of interconnection line resources in the programmable logic device FPGA is measured by an interconnection test method, so that the dynamic power consumption of interconnection lines in the winding resource FPGA of the programmable logic device can be accurately measured, and the accuracy of a power consumption analysis and evaluation EDA tool software model of the programmable logic device is improved.

Description

Technical field [0001] The present application relates to the field of programmable logic devices, in particular to a dynamic power consumption test device and method for programmable logic devices. Background technique [0002] Programmable logic devices are a semi-customized circuit in the field of dedicated integrated circuits, which has developed rapidly in recent years. As the FPGA size is increasing, the problem of reliability brought by chip power and fever is increasingly valued. The FPGA's power consumption affects the power design and heat dissipation scheme of its working system, which requires power analysis and testing during the project design. [0003] In the existing FPGA power modeling method, the theoretical model is established according to the equivalent load and driving load number of the interconnect, or the interconnect power consumption is derived into other unit module logic resources, and it is not separately modeled. And measured. When constructing a po...

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Problems solved by technology

[0004] The present application provides a dynamic power consumption test device and method for programmable logic devices to solve the problem of accurately measuring the dynamic power consumption of interconnection wires when testing the winding resource vectors of programmable logic devices in the existing construction power consumption The problem

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