Chip sealing ring

Abstract

The invention provides a chip sealing ring which comprises a first metal layer to an Nth metal layer which are sequentially formed on a substrate, the N metal layers are separated through dielectric layers, each metal layer comprises a first metal strip to an Nth metal strip, the first metal strip to the Nth metal strip in the same metal layer sequentially surround the chip to form N non-closed annular structures from inside to outside, each metal strip is provided with a first opening, and each metal strip of each metal layer is communicated to one metal strip of the adjacent layer; the metal strips of the same metal layer cannot be communicated to the same metal strip; and the chip sealing ring also comprises a plurality of electrical property test keys used for testing the electrical property of the metal layer, and each metal strip is provided with two electrical property test keys. The electrical parameters of the metal layer communicated with the electrical test key are obtained by testing the signal of the electrical test key.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a chip sealing ring. Background technique [0002] In the wafer packaging process, chips need to be cut. In order to protect the chip, a chip sealing ring (seal ring) is generally arranged between the chip and the dicing line. The chip sealing ring can prevent any cracks from intruding into the chip, and part of the structure of the chip sealing ring is an interlayer dielectric layer (IMD). [0003] In the semiconductor industry, it has been a research direction to obtain more chips per unit wafer. The methods generally adopted in the prior art are to reduce the width of the dicing line or omit the sealing ring structure of the chip, and reduce the area of ​​parts other than the chip, so that there is more area to form the chip, so as to increase the number of chips on the wafer. But because there are enough electrical test keys to be placed on the cutting line, and eve...

AI Technical Summary

Problems solved by technology

Therefore, if the width of the cutting line is blindly reduced, it may cause the electrical test key to be unable to be placed or affect the function of the electrical test key

However, if the chip sealing ring is omitted, it may bring the risk of subsequent cutting collapse

Regardless of the advanced 28nm process or the ordinary 0.18μm process, there have been many cases of chip cracking. The results of failure analysis are generally that when the dicing line is cut, the mechanical force generated breaks through the protection of the chip sealing ring, making the chip The sealing ring produces cracks, and the cracks extend to the inside of the chip, resulting in disconnection and damage to the circuit inside the chip. Therefore, the chip sealing ring is indispensable

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