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Address fast reading circuit and method

A technology for reading circuits and addresses, which is applied in televisions, electrical components, color TVs, etc., can solve the problems of increasing the number of encoding circuits, affecting the working frequency of circuits, and increasing the difficulty of layout and wiring, etc. Effect of high readout speed and signal propagation speed

Pending Publication Date: 2022-01-25
西北工业大学太仓长三角研究院 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The main disadvantage of the existing address readout method is that when the array reaches a certain scale, the number of stages of the encoding circuit increases
For example: if an array has 1024 channels and needs to read address information, according to the existing method, five-level circuits are required to read the address, the propagation path is complicated, and it takes more time to propagate the address, which affects the operating frequency of the circuit
And in the deep submicron process, complex lines will further increase the difficulty of layout and wiring

Method used

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  • Address fast reading circuit and method
  • Address fast reading circuit and method
  • Address fast reading circuit and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0036] This embodiment provides a fast address readout circuit, which includes multiple groups of channels, and each group of channels has the same circuit connection structure;

[0037] Each group of channels integrates address control registers and pull-up and pull-down units. The configuration of the pull-up and pull-down units in each group of channels is different. The channel hit signal in each group of channels is calculated and transmitted to the lower-level code as the chip select signal of this group. circuit, the lower coding circuit transmits the chip selection signal step by step in the same way;

[0038] Each group of channels is provided with a tri-state buffer as a control switch, the tri-state buffer controls the output state of the address data, the control latch latches the hit signal and controls the on-off state of the tri-state buffer.

[0039] In this embodiment, when the pull-up and pull-down units are reset, address data is configured, and after reset,...

Embodiment 2

[0054] For this example, see the attached image 3 , image 3 It is shown as the overall block diagram of the fixed 6bit address of the first-level circuit. The low-bit address readout circuit is divided into K / 64 groups, and the overall circuit level is suitable for circuits with 256 channels and above.

[0055] Taking a circuit with 1024 channels as an example, there are 16 first-level low-bit address readout circuits, 4 second-level encoding circuits, and a total of three levels for the overall circuit.

[0056] The reset signal is low effective. When resetting, use the pull-up and pull-down unit to configure the address bits of the module. ADDR_1ST[5:0] in the figure is the address bits of each channel. The readout circuit module contains 64 channels and 384 address bits, which are simplified in the figure, and the hit signal is the same.

[0057] When a hit occurs, the corresponding channel address bit value is output as the lower 6-bit address and transmitted to the pe...

Embodiment 3

[0059] For this example, see the attached Figure 4 , the internal circuit of the channel is expanded.

[0060] Taking the fixed 6bit address register size as an example, each first-level low-order address readout circuit module contains 64 channels. When resetting, the channel corresponds to the address. For example, CH0 corresponds to 000000, and CH63 corresponds to 111111. Change.

[0061] When a hit occurs, the switch is turned on, and the output is in a high-impedance state to prevent bus competition. When a hit occurs, the switch is turned off, and the output address data is output to the peripheral circuit as the low address ADDR_1ST.

[0062] At the same time, the chip select signal CS_1ST generated by each hit signal is transmitted to the secondary encoding circuit through OR operation. If only the primary low address readout structure is used as the overall readout structure, this signal does not need to be generated.

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Abstract

The invention relates to an address fast reading circuit and method. The address fast reading circuit comprises a plurality of groups of channels, and each group of channel circuit has the same connection structure; a control latch and a pull-up and pull-down unit are integrated in each group of channels, the configuration modes of the pull-up and pull-down units are different, channel hit signals of each group of channels are operated and then are transmitted to a lower-stage coding circuit as chip selection signals of the group, and the chip selection signals are transmitted step by step by the lower-stage coding circuit in the same mode; each group of channels is provided with a three-state buffer as a control switch, address transmission delay is remarkably reduced and address reading speed is accelerated by integrating a control latch in the channel and directly reading values of a pull-up and pull-down unit, and a reading circuit is integrated in the channel to serve as a standard module or IP processing, so that multiplexing of a module circuit is facilitated and the chip array is easy to expand, a low-order address is quickly read out by setting a pull-up and pull-down unit in a channel, and a high-order address is obtained by combining a hierarchical address coding scheme, so that the power consumption requirement is ensured.

Description

technical field [0001] The invention relates to the technical field of circuit design, in particular to a fast address readout circuit and a readout method. Background technique [0002] The address readout circuit is a common circuit for information detection, which is used to obtain the position information of arrays such as images and particle trajectories. After the sensor array is hit, the hit information is transmitted to the digital circuit after the analog circuit is amplified and shaped, and the hit position information is encoded by the digital circuit through multi-levels to obtain the corresponding address, and is carried out under the control of the peripheral circuit. read out. As medical imaging, particle detection and other fields have higher and higher requirements for the accuracy of position information, and the array scale is getting larger and larger, the readout time and area size of the traditional address readout circuit structure are difficult to me...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N5/378
CPCH04N25/75
Inventor 王佳张浩楠魏晓敏郑然薛菲菲胡永才
Owner 西北工业大学太仓长三角研究院