FPGA time sequence simulation verification method and device based on MATLAB

Abstract

The invention belongs to the technical field of FPGA simulation verification technology, and provides an FPGA time sequence simulation verification method and device based on MATLAB. The method comprises the following steps: S1, reading a script file, a test case file and a test platform file, and establishing a time sequence simulation environment; S2, loading an FPGA design netlist file and a simulation program; S3, reading a simulation result file and a simulation log file obtained by time sequence simulation; S4, comparing the simulation result file with an expected result file, if the simulation result file is consistent with the expected result file, entering a step S5, and if the simulation result file is inconsistent with the expected result file, judging that the result is not passed and entering a step S5, judging whether errors and warning contents in the simulation log file pass or not; and S6, outputting an FPGA time sequence simulation verification result according to a judgment result. By adopting the method, the whole time sequence simulation work can be automatically completed, the workload of verification personnel is greatly reduced, the manual error risk is reduced, and the airworthiness conformity of products is guaranteed.

Description

technical field [0001] The invention relates to the technical field of FPGA simulation verification, in particular to a MATLAB-based FPGA timing simulation verification method and device. Background technique [0002] With the continuous development of microelectronics technology and EDA technology, FPGA is more and more applied to airborne electronic equipment due to its high integration, small size, and low power consumption. Modifying the hardware logic description can change the purpose of the hardware design, thus bringing great flexibility to the hardware design. However, potential flaws or errors may arise in the logic design, which will lead to failure of components and systems, and even pose a safety threat to the aircraft. [0003] DO-254 is an industry guideline proposed to solve this type of problem and ensure that FPGAs pass airworthiness certification. It emphasizes the importance of FPGA verification. High-coverage and high-confidence verification activities...

AI Technical Summary

Problems solved by technology

In the current timing simulation activities, there is still a lot of manual participation, the workload is complicated and most of them are repetitive physical activities. On the one hand, it takes up the time of engineers for creative work. On the other hand, repetitive activities are easy to cause fatigue and reduce the Efficiency and accuracy are not conducive to the final airworthiness compliance review

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