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Data packet routing method for on-chip message network

A message network and data packet technology, applied in the field of data packet routing of on-chip message network, to achieve the effect of occupying less chip resources, less connection lines, and less power consumption

Pending Publication Date: 2022-02-08
苏州暴雪电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Whether it is the design of the bus and switch, or the flow processor, there is no way to fundamentally change the non-scalability of the design of multi-core or even many-core processors.

Method used

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  • Data packet routing method for on-chip message network
  • Data packet routing method for on-chip message network
  • Data packet routing method for on-chip message network

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Embodiment Construction

[0062] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0063] 1. The on-chip multi-core or many-core structure applied in this design scheme is as follows:

[0064] 1. In many cores on a chip, each processor has a unique address, and the address of each processor is different. The address of the processor is a number whose bit width is determined by the number of all processors in the many-core on-chip. For example, if there are 256 processors on the chip, the processor address must be at least 8 bits wide.

[0065] 2. Each processor is placed in a hierarchical grouping manner. That ...

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PUM

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Abstract

The invention discloses a data packet routing method for an on-chip message network, which adopts many measures to improve the transmission speed. For example, a bottom-layer switch, such as a first-level switch and a second-level switch, directly forwards without cache; the high-level switch can adopt a multi-channel mode to solve the communication bottleneck; and a multi-dimensional network-on-chip can also be established to further improve the transmission speed. And layered implementation of an on-chip network communication protocol is supported. By using the network layer data packet routing forwarding method provided by the invention, the number of connecting lines of the network-on-chip is as small as possible, the occupied chip resources are as small as possible, and the power consumption is low.

Description

technical field [0001] The invention relates to the technical field of processors, in particular to a data packet routing method for an on-chip message network. Background technique [0002] Power consumption and manufacturing process issues limit the development of single-core processors to continuously improve performance. The main frequency of single-core is approaching the limit. Multi-core or many-core technology is the most effective way to improve processor performance while reducing power consumption. [0003] However, when more and more processor cores are integrated on a single chip, how to ensure high-efficiency communication between each processor core becomes an important issue. [0004] The design of multi-core or many-core processors can be roughly divided into three categories: bus or switch interconnect design, stream processor and graphics processor, and network interconnect processor. The advantages of a multi-core design with a bus or a switch as the bas...

Claims

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Application Information

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IPC IPC(8): H04L49/25H04L49/00H04L49/109
CPCH04L49/25H04L49/30H04L49/109
Inventor 秦晓阳徐培欣
Owner 苏州暴雪电子科技有限公司