Multi-frequency synchronous clock system and method

Abstract

The invention discloses a multi-frequency synchronous clock system which comprises a first clock chipset, a second clock chipset,..., a Kth-stage clock chipset and a last-stage clock chipset which are cascaded, wherein the first-stage clock chip set is connected with an external clock, and the second-stage clock chip set, the third-stage clock chip set and the last-stage clock chip set respectively comprise a plurality of clock chips to form a clock signal transmission network; all clock chips in the second to K-level clock chip groups work in a non-frequency-division state; the system further comprises a signal synchronization module. A plurality of last-stage synchronization modules are arranged between the Kth-stage clock chipset and the last-stage clock chipset, each last-stage synchronization module comprises a buffer, a trigger and a phase-locked loop, and the trigger adjusts and locks the phase relation between a clock signal and a synchronization signal; and all the clock chips in the last-stage clock chip group output the clock signals in a frequency division manner under the control of the synchronous signals. According to the invention, the output of multi-channel clocks with different frequencies is realized, and the outputs of all clocks are kept synchronous.

Description

technical field [0001] The invention relates to a clock system design method, in particular to a multi-frequency synchronous clock system and a method for generating a multi-frequency stable synchronous clock. Background technique [0002] In the software-based radar digital TR component system, there are more and more DAC and ADC channels, and the realization of RF direct sampling requires higher and higher sampling rates for ADCs and DACs. Based on the difference in data processing pressure, the operating frequency requirements of ADCs and DACs are different. Not all are the same. In order for the software-based radar to accurately identify targets, it is necessary to ensure that all DAC channels in the system are kept in sync, all ADC channel acquisitions are also kept in sync, and the DAC output and ADC acquisition are also kept in sync. The key to achieving the above process is that all clocks in the system A synchronized state must be reached. The usual method uses h...

AI Technical Summary

Problems solved by technology

The usual method uses high-frequency clock buffer (cache) for cascading. Since the high-frequency clock is susceptible to interference, it is difficult to adjust the sampling synchronization, the adjustment accuracy is low, and the number of channels is limited. At the same time, due to the influence of high and low temperature, unstable Clock synchronization will lead to ADC and DAC synchronization state drift, which will affect the radar beam pointing and eventually lead to radar performance deterioration

Images