Virtual memory management method and device supporting physical address larger than virtual address

Abstract

The invention discloses a virtual memory management method and device supporting a physical address larger than a virtual address. The method comprises the following steps: determining a target virtual address corresponding to an instruction fetching address or a memory access address in any one of a user mode, a supervision mode or a machine mode; a target physical address corresponding to a target virtual address is determined by accessing a virtual memory management unit, page table entries for mapping the virtual address to the physical address are built in the virtual memory management unit, and the bit width of the target virtual address may be smaller than or equal to the bit width of the target physical address, especially in the field of many-core application; and finally, the target physical address is returned to the corresponding fetch unit or memory access unit, and correctness and validity are ensured. By adopting the embodiment of the invention, the address translation from the virtual address to the physical address can be completed under the condition that the bit width of the virtual address is smaller than the bit width of the physical address, the many-core architecture can be ensured to effectively work in various modes such as a user mode, a supervision mode and a machine mode, and the applicability is high.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to a virtual memory management method and device that support a physical address larger than a virtual address. Background technique [0002] Any computer system with a certain complexity relies on the cooperative work of multiple processes running on the processor. Since each instruction has its own virtual address, it is necessary to complete the conversion from virtual address to physical address. [0003] Although in most processor architectures, the virtual address bit width is generally not smaller than the physical address bit width, in some cases there will be a problem that the virtual address bit width is smaller than the physical address bit width, such as the Sv39 mode in the RISC-V architecture (39-bit page memory management architecture provided for 64-bit systems with RISC-V structure) and Sv48 mode (48-bit page memory management architecture provided for 64-bit sys...

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Problems solved by technology

[0003] Although in most processor architectures, the virtual address bit width is generally not smaller than the physical address bit width, in some cases there will be a problem that the virtual address bit width is smaller than the physical address bit width, such as the Sv39 mode in the RISC-V architecture (39-bit page memory management architecture provided for 64-bit systems with RISC-V structure) and Sv48 mode (48-bit page memory management architecture provided for 64-bit systems with RISC-V structure) there are virtual address bit widths less than The problem of the bit width of the physical address can easily lead to system errors or even crashes during the address translation process

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