System architecture and peripheral communication method for soc chip

Abstract

The application relates to the technical field of integrated circuit data transmission, and discloses a system architecture for a SoC chip, including: a processor for executing an erase command or a programming command for an external memory; the external memory is connected to the processor through an AHB bus; The on-chip RAM is connected to the processor and external memory through the AHB bus; the IRB bus is connected to the on-chip RAM; the IRB bus is used to coordinate the communication sequence between the first on-chip peripheral and the on-chip RAM. In this way, when the processor executes the erase instruction or prog programming instruction on the external memory, although the AHB bus is pulled low, the on-chip peripherals can communicate with the on-chip RAM through the IRB bus, so that the SoC chip can respond in time. Set, thereby improving the speed of the soc chip to respond to the on-chip peripherals. The application also discloses a peripheral device communication method.

Description

technical field [0001] The present application relates to the technical field of integrated circuit data transmission, for example, to a system architecture and a peripheral communication method for a soc chip. Background technique [0002] With the iterative development of soc (System on Chip, system-on-chip) chips, the performance of soc chips has attracted more and more attention from users. A typical AMBA (Advanced Microcontroller BusArchitecture, Advanced Microcontroller Bus Architecture) system architecture is usually set in the soc chip for data interaction. like figure 1 As shown, a typical AMBA system architecture includes AHB (Advanced High Performance Bus) bus 5, APB (Advanced Peripheral Bus, peripheral bus) bus 11, bridge 12, processor 1, on-chip RAM (Random Access Memory, Random access memory) 3, second DMA (Direct Memory Access, direct memory access) controller 9, external memory 2, SPI (Serial Peripheral Interface, serial peripheral interface) communication ...

AI Technical Summary

Problems solved by technology

In the related art, when the AMBA system executes the erase instruction or the prog programming instruction to the external memory, the AHB bus is pulled low, so that on-chip peripherals such as the SPI communication interface, UART interface, TIMER interface and GPIO interface cannot pass through the AHB bus Communicate with on-chip RAM, causing the soc chip to respond slowly to on-chip peripherals

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