Semiconductor package device and manufacturing method thereof

A technology of packaging device and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, semiconductor device, semiconductor/solid-state device components and other directions, can solve the problems of through-silicon hole wear affecting the electrical connection performance of through-silicon holes, etc., to ensure electrical connection. performance effect

Pending Publication Date: 2022-04-05
ADVANCED SEMICON ENG INC
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  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

The above-mentioned TSVs are too worn or difficult to expose,

Method used

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  • Semiconductor package device and manufacturing method thereof
  • Semiconductor package device and manufacturing method thereof
  • Semiconductor package device and manufacturing method thereof

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Embodiment Construction

[0031] The specific implementation manners of the present disclosure will be described below in conjunction with the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects produced through the contents recorded in this specification. It should be understood that the specific embodiments described here are only used to explain related inventions, rather than to limit the invention. In addition, for the convenience of description, only the parts related to the related invention are shown in the drawings.

[0032] It should be noted that the structures, proportions, sizes, etc. shown in the accompanying drawings of the specification are only used to match the content recorded in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present disclosure. There are limited conditions, so it has...

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Abstract

The invention relates to a semiconductor packaging device and a manufacturing method thereof. The semiconductor packaging device includes: a molding material; the bridging chip is wrapped in the molding material, the bridging chip is provided with a conductive pad and a first conductive hole, the conductive pad is located on the first surface of the bridging chip, and the first conductive hole is located in the bridging chip and electrically connected with the conductive pad; the buffer layer is arranged on the first surface of the bridging chip, a second conductive hole is formed in the buffer layer, the first end of the second conductive hole is electrically connected with the conductive pad, and the second end of the second conductive hole is exposed out of the buffer layer. According to the semiconductor packaging device, the problem that the silicon through hole is excessively abraded or is difficult to expose due to warping of the semiconductor packaging device in the grinding process can be avoided, and the electrical connection performance between the semiconductor packaging device and the outside can be guaranteed.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging device and a manufacturing method thereof. Background technique [0002] FOCoS (Fan Out Chip on Substrate) packaging technology is implemented by using a fan-out composite chip on a typical ball grid array substrate. It can provide a lower cost solution with, in practice, better electrical and thermal performance than silicon interposer structures. [0003] Figure 1A It is a schematic diagram of a FOCoS semiconductor packaging device. Such as Figure 1A As shown, the molding material 13 is covered with the bridge chip 11 and the electronic component 12 . The bridge chip 11 is electrically connected to the electronic component 12 . Through silicon vias (Through Silicon Via, TSV) 14 are disposed in the bridge chip 11 . The TSV 14 is used for external connection. Usually from the bottom side of the bridge chip 11 (correspondin...

Claims

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Application Information

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IPC IPC(8): H01L23/538H01L25/065H01L21/50
Inventor 叶上暐黄敏龙吴崇熙杨盛文张谦维
Owner ADVANCED SEMICON ENG INC
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