Packaging structure and manufacturing method

Abstract

The invention provides a packaging structure and a manufacturing method. The packaging structure comprises a lower packaging body and an upper packaging body which are electrically connected, the lower packaging body comprises a prefabricated interconnected silicon core stacking structure and a first plastic packaging layer surrounding the periphery of the prefabricated interconnected silicon core stacking structure; the prefabricated interconnected silicon core stacking structure comprises a silicon interconnection layer, and the silicon interconnection layer comprises a first surface and a second surface which are opposite to each other; a back-end rewiring stacking layer and a first prefabricated rewiring stacking layer are stacked on the first surface, and the back-end rewiring stacking layer is electrically connected with the first prefabricated rewiring stacking layer; a passivation layer is arranged on the second surface; the silicon interconnection layer comprises a silicon substrate and a plurality of first pre-conduction columns embedded in a plurality of silicon through holes in the silicon substrate, each first pre-conduction column comprises a first end and a second end which are opposite to each other, the first end is exposed from the first surface, and the second end is exposed from one side, far away from the second surface, of the passivation layer; the upper packaging body is arranged above the first prefabricated redistribution stacking layer and is electrically connected with the first prefabricated redistribution stacking layer.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, in particular to a packaging structure and a manufacturing method. Background technique [0002] The rapid development of high-speed computing and artificial intelligence has put forward higher requirements for the packaging of semiconductor chips and packages, especially for packaging substrates, which usually require packaging substrates to have narrower line width / line spacing, more Good voltage drop control. The line width / line spacing of traditional laminated substrate wiring is usually around 15um / 15um, which is increasingly unable to meet the high-density packaging requirements of electronic components used in high-speed computing and artificial intelligence. [0003] In addition, the traditional laminated substrate technology is 1) the supply of stacked dielectric materials; 2) the manufacturing cycle; 3) the wiring with a line width of less than 10um and the yield contro...

AI Technical Summary

Problems solved by technology

The line width / line spacing of traditional laminated substrate wiring is usually around 15um / 15um, which is increasingly unable to meet the high-density packaging requirements of electronic components used in high-speed computing and artificial intelligence.

[0003] In addition, the traditional laminated substrate technology is 1) the supply of stacked dielectric materials; 2) the manufacturing cycle; 3) the wiring with a line width of less than 10um and the yield control of embedded chips; 4) the gap between substrate thickness and hardness There are great difficulties in balance and other aspects

[0004] Therefore, it is necessary to propose a new packaging structure and preparation method to overcome the traditional laminated substrate due to factors such as thickness, line width and line spacing, which cannot meet the needs of high-density packaging for electronic components used in high-speed computing and artificial intelligence.

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