Manufacturing method of semiconductor structure

Abstract

The invention provides a method for manufacturing a semiconductor structure, which comprises the following steps of: providing a substrate which comprises a plurality of bit line structures with contact holes formed between adjacent bit line structures; forming an initial contact layer in the contact hole, wherein the initial contact layer comprises a gap; etching the initial contact layer, and removing part of the initial contact layer to form a first contact layer; etching the first contact layer to remove part of the gap, and forming a second contact layer by the retained first contact layer; the second contact layer is etched, the etching rate of the concave side wall is larger than the etching rate of the concave bottom, so that the remaining gap is removed, and a third contact layer is formed. According to the invention, the initial contact layer is etched for multiple times, and the etching speed of the side position of the second contact layer is controlled to be greater than the etching speed of the middle position of the second contact layer, so that the contact layer with the planarized top morphology is formed, and the yield and the conductivity of the semiconductor structure are improved.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor structure. Background technique [0002] With the continuous development of dynamic random access memory (Dynamic Random Access Memory, DRAM) process technology, the distance between adjacent bit line structures is getting smaller and smaller. As the spacing between adjacent bit line structures becomes smaller, it becomes more and more difficult to manufacture the contact holes formed between the bit line structures, especially when forming contact holes with high aspect ratios, the filling in the contact holes is used to form There will be gaps in the material of the contact layer, and the top shape of the contact layer in the contact hole is difficult to control, thereby reducing the conductivity and yield of the semiconductor structure. Contents of the invention [0003] The following is an overview of the subject m...

AI Technical Summary

Problems solved by technology

As the spacing between adjacent bit line structures becomes smaller, it becomes more and more difficult to manufacture the contact holes formed between the bit line structures, especially when forming contact holes with high aspect ratios, the filling in the contact holes is used to form There will be gaps in the material of the contact layer, and the top shape of the contact layer in the contact hole is difficult to control, thereby reducing the conductivity and yield of the semiconductor structure

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