Integrated micro-channel optimization method based on complex power distribution
An optimization method and micro-channel technology, applied in design optimization/simulation, instrumentation, calculation, etc., can solve the problem that the size of micro-channel cannot be obtained, the performance optimization of micro-channel takes a long time, and the applicability of micro-channel optimization is limited. problems, to achieve the effect of improving optimization efficiency and optimization applicability, overcoming optimization limitations, and reducing volume ratio
Active Publication Date: 2022-04-22
XIDIAN UNIV
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However, the disadvantage of this method is that because the method is modeled and simulated in the simulation software, it takes a long time to optimize the performance of the microchannel.
However, the disadvantage of this method is that it is based on micro-scale micro-channel topology optimization, and in practice the power distribution of the chip has a major impact on it. Therefore, this method is not suitable for micro-channels with complex power distribution. Obtaining the optimal microchannel scale leads to limitations in the applicability of microchannel optimization
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[0051] The present invention will be described in further detail below in conjunction with specific examples, but the embodiments of the present invention are not limited thereto.
[0052] Such as figure 1 As shown, the optimization method of a kind of integrated micro-channel based on complex power distribution provided by the present invention comprises:
[0053] Step 1: Obtain the physical model of the 3D integrated chip;
[0054] Wherein, the physical mold is composed of a plurality of silicon-based layers stacked in the vertical direction, and a plurality of micro-channels are etched in each silicon-based layer, and there is a device layer and an interconnection layer between two silicon-based layers from top to bottom;
[0055] The circuit physical model of a three-dimensional integrated chip such as figure 2 , figure 2 It consists of three silicon layers stacked in the vertical direction. The silicon layer in a three-dimensional integrated circuit is composed of an...
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According to the integrated micro-channel optimization method based on complex power distribution, grids are divided for a three-dimensional integrated micro-channel, a mathematical model of the equivalent thermal conductivity of a single grid calculation unit is constructed, and the equivalent thermal conductivity of the three-dimensional integrated micro-channel is calculated based on collaborative optimization of intra-layer power distribution and micro-channel geometric parameters. And calculating the optimal geometric parameters for effectively reducing the intra-layer peak temperature and the volume ratio of the micro-channel so as to optimize the size of the micro-channel and obtain the accurate size of the micro-channel. According to the invention, the problems of overhigh peak temperature caused by complex power distribution in an existing three-dimensional integrated circuit layer and overlarge volume ratio of a traditional micro-channel can be solved, and the applicability of micro-channel optimization is improved.
Description
technical field [0001] The invention belongs to the technical field of electronic circuits, and in particular relates to an optimization method of an integrated microfluidic channel based on complex power distribution. Background technique [0002] A three-dimensional integrated circuit stacks and interconnects multiple chips in a vertical direction through TSV (Thermal Silicon Via, through-silicon via), thereby reducing interconnection delay and power consumption. Compared with traditional integrated circuits, TSV can realize vertical interconnection communication between layers and effectively shorten the length of interconnection lines. [0003] As the size of the chip becomes smaller and smaller, the power consumption density of the chip increases significantly. The chip is affected by the back end of line (BEOL) and the bonding layer (Bonding Layer) with poor thermal conductivity, which hinders the heat transfer between the layers and makes it easier to accumulate heat...
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Login to View More IPC IPC(8): G06F30/20G06F30/3308G06F119/08
CPCG06F30/20G06F30/3308G06F2119/08Y04S10/50
Inventor 董刚宋栋梁王洋朱樟明杨银堂
Owner XIDIAN UNIV