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Precise reconstruction of panel-level packages

A bare die, sub-block technology, applied in the field of precise reconstruction of panel-level packaging, which can solve problems such as yield reduction

Pending Publication Date: 2022-04-22
新加坡PYXIS CF私人有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This misalignment of downstream processes results in lower yields

Method used

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  • Precise reconstruction of panel-level packages
  • Precise reconstruction of panel-level packages
  • Precise reconstruction of panel-level packages

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Experimental program
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Embodiment 1

[0027] Embodiments generally relate to panel level packaging devices, such as panel level packaging semiconductor devices or integrated circuits (ICs). In particular, the application relates to high precision bonding of die or devices on a panel for panel level packaging.

[0028] figure 1 A simplified top view of semiconductor wafer 100 is shown. The wafer may be a lightly doped p-type silicon wafer. Other types of wafers may also be used. For example, the wafer may be a silicon carbide (SiC) wafer, gallium nitride (GaN) wafer, gallium arsenide (GaAs) wafer, or indium phosphide (InP) wafer. Devices 110 are formed on the active surface of wafer 100 in parallel. The active surface may be the upper surface of wafer 100 . The passive surface can be the lower surface of the wafer.

[0029] The devices 110 are arranged in rows along a first direction (x) and in columns along a second direction (y). After processing the wafer is complete, the wafer is diced along dicing or sa...

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PUM

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Abstract

The invention relates to a panel-level package (PLP) with high positioning accuracy of dies. The PLP accurately binds the die to the die binding area of the alignment panel. High precision is achieved by providing a die bonding area with a local alignment mark. Precise binding of dies on an alignment carrier results in a reconstructed wafer with precise die positioning. The dies of the reconstructed wafer may be scanned by a die position check (DLC) scan based on die sub-blocks, thereby achieving high throughput of DLC. The DLC scans to generate a DLC file, wherein the DLC file comprises coordinate points of sub-blocks of the reconstructed wafer. In addition, a laser direct imaging (LDI) file may be generated using the sub-block circuit file aligned with the DLC file. The use of sub-block circuit files facilitates high throughput of generating LDI files with high precision since the reconstituted wafer is formed using an alignment carrier with local alignment marks.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of S.G. Provisional Application No. 10202009834T, filed October 2, 2020, and is a continuation-in-part of pending U.S. Patent Application Serial No. 16 / 814,861, filed March 10, 2020, and the U.S. Patent Application No. 16 / 814,861 claims the benefit of S.G. Provisional Application No. 10201902757X, filed March 27, 2019, all of which are hereby incorporated by reference in their entirety for all purposes. technical field [0003] This application relates to precise reconfiguration of panel level package devices. In particular, the application relates to the bonding of dies on panels for high precision panel level packaging. Background technique [0004] Panel-level packaging (PLP) of devices has attracted great interest in recent years. This is due to the larger volume of die that can be packaged in parallel compared to conventional wafer-level or substrate-level packaging techniques...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/68H01L21/56H01L23/544
CPCH01L21/56H01L23/544H01L21/682H01L2223/54426
Inventor 阿姆兰·森建顺·蔡关青峰伟豪·李
Owner 新加坡PYXIS CF私人有限公司