PTP master clock device, clock synchronization method and storage medium

Abstract

According to the PTP master clock device, the clock synchronization method and the storage medium provided by the embodiment of the invention, each NIC sends the timestamp of the event message to the corresponding VNIC, one VNIC of a processor only receives the sending timestamp of one sync message, the message is generated based on the processor, and the timestamp is recorded based on the FPGA, so that a complete 1588 protocol stack can be realized. The processor undertakes the message generation logic, so that the occupation amount of FPGA resources is reduced; and compared with the FPGA, the message generation logic of the processor is easier to realize, and the workload of realizing the complete 1588 protocol stack is reduced.

Description

technical field [0001] The present application relates to the technical field of communication, in particular to a PTP master clock device, a clock synchronization method and a storage medium. Background technique [0002] The fronthaul interface in the mobile communication base station has multiple FPGA (Field-Programmable GateArray, Field Programmable Gate Array) clock synchronization requirements between boards. When the fronthaul interface uses packet switching, the 1588 protocol can be used, that is, the PTP protocol ( Precision Clock Synchronization Protocol) to achieve synchronization. The protocol has the following functions: initial configuration of the master and slave side, grouping and sending and receiving of PTP messages, selection of the master clock (slave clock side function), extraction of time stamp, calculation of time offset and delay, clock State machine management, frequency phase adjustment, etc. The hardware needs to have a counter that provides ti...

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Problems solved by technology

[0005] against figure 2 As shown in the hardware design, in the prior art, the software part of the 1588 protocol stack is implemented with logic on the FPGA, but based on the logic implementation characteristics of the FPGA, this solution needs to occupy a large amount of FPGA resources and realize the work of the complete 1588 protocol stack a lot

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