Pulse compression method for saving FPGA RAM resources

Abstract

The invention discloses a pulse compression method capable of saving FPGA (Field Programmable Gate Array) RAM (Random Access Memory) resources, which comprises the following steps of: inputting echoes received by a radar system into an FFT (Fast Fourier Transform) IP (Intellectual Property) core, configuring processing points required by FFT, and selecting data to be output according to a bit inverted sequence; reading a matched filtering coefficient in an inverted sequence, and then carrying out complex multiplication on the matched filtering coefficient and an output result of the FFT IP core; and the inverse sequence complex multiplication result after complex multiplication is input into an IFFT module, IFFT is calculated by using a frequency domain extraction calculation method, an IFFT result of positive sequence output is obtained, and pulse compression is completed. By adopting the frequency domain extraction IFFT processing method, inverse sequence input and positive sequence output can be achieved through IFFT, the defect that an FFTIP core can only achieve positive sequence input is overcome, therefore, additional RAM resources do not need to be used for conversion from the inverse sequence to the positive sequence, the RAM resources needed to be used by an FPGA are saved, meanwhile, due to the fact that the data sequence conversion process is reduced, the data conversion efficiency is improved, and the data conversion efficiency is improved. And the operation rate of the pulse compression algorithm can be improved, the signal processing operation time is shortened, and the real-time performance of the radar is improved.

Description

technical field [0001] The invention belongs to the field of digital signal processing, and in particular relates to an FPGA realization method of pulse compression. Background technique [0002] In the design of the radar system, in order to meet the requirements of detection distance and distance resolution at the same time, it is necessary to transmit a stretched pulse and then perform pulse compression to realize it. In the actual radar signal processing, pulse compression usually adopts the method of pulse compression in frequency domain, and performs FFT / IFFT transformation and multiplication operation in FPGA. [0003] The key to the implementation of pulse compression lies in the calculation of FFT and IFFT. FFT / IFFT is traditionally implemented using the FFT IP core. Data can only be input in positive sequence. In order to obtain the output result in positive sequence, additional RAM resources are needed for conversion. ; But with the improvement of radar processin...

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Problems solved by technology

[0003] The key to the implementation of pulse compression lies in the calculation of FFT and IFFT. FFT / IFFT is traditionally implemented using the FFT IP core. Data can only be input in positive sequence. In order to obtain the output result in positive sequence, additional RAM resources are needed for conversion. ; But with the improvement of radar processing performance, more and more points need to be processed by pulse compression, so the number of FFT points is getting larger and larger, more and more RAM resources are used, and the difficulty of signal processing is increasing

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