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Linear codec based on in-memory calculation of nonvolatile memory and method thereof

A non-volatile memory and codec technology, applied in static memory, read-only memory, information storage, etc., can solve the problem of high overall power consumption, and achieve the effect of reducing power consumption and delay

Pending Publication Date: 2022-05-10
BEIHANG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, due to the high threshold voltage requirement of this device, the overall power consumption is still high

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  • Linear codec based on in-memory calculation of nonvolatile memory and method thereof
  • Linear codec based on in-memory calculation of nonvolatile memory and method thereof
  • Linear codec based on in-memory calculation of nonvolatile memory and method thereof

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Embodiment Construction

[0039] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0040] A linear code is a linear error-correcting code consisting of data bits and parity bits. In a linear code block, the length of the parity bits is k. In order to implement the error correction function, the length of the linear code is at most 2 k -1, the length of data bits is at most 2 k -1-k.

[0041] The structure of two-port nonvolatile memory and three-port nonvolatile memory is as follows Figure 1-2 shown. For a two-port nonvolatile memory, ...

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Abstract

The invention discloses a linear codec based on in-memory calculation of a nonvolatile memory and a method thereof. The codec comprises a memory array and a calculation module, the storage array is connected with the calculation module; the method comprises the following steps: loading a generation matrix H1 or a parity check matrix H2, converting a data bit d or a code word r which needs to be coded into binary voltage, correspondingly applying the binary voltage to N bit lines BL according to a time sequence, and enabling the binary voltage to flow into M three-port nonvolatile memories in a calculation module after passing through a storage array; wherein the code word r is a code word obtained after coding; m three-port nonvolatile memories in the calculation module judge whether the turning of the resistance state needs to be completed or not according to the current generated by the storage array. The power consumption overhead is effectively reduced, and the delay is reduced.

Description

technical field [0001] The present invention relates to the field of computer technology, and more specifically relates to a linear codec based on non-volatile memory in-memory calculation and a method thereof. Background technique [0002] A linear code is a linear error correcting code (Error Correcting Code, ECC for short) widely used in memory and communication systems. The encoding / decoding of information needs to be realized by encoding and decoding hardware. However, the existence of data transmission between the memory and the codec hardware makes the process of encoding and decoding face serious power consumption problems. [0003] In order to solve the power consumption problem caused by data transmission, in-memory computing technology has attracted widespread attention. overall performance. In recent years, a variety of IMC (In-Memory-Computing, IMC) paradigms based on memory devices have been proposed, such as spintronic devices, resistance devices, and phase...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/30G11C16/10G11C16/08G11C16/24
CPCG11C16/30G11C16/10G11C16/08G11C16/24
Inventor 蒋林君张和康旺
Owner BEIHANG UNIV