Three-dimensional memory and manufacturing method thereof

Abstract

The invention relates to a three-dimensional memory, a manufacturing method thereof and a storage device. The method includes: forming a first stack block; forming a first step structure on the first stacking block; forming a second stacking block on one side of the first stacking block along the stacking direction of the first stacking block; a first step structure is formed on the first stacking block, a second step structure is formed on the second stacking block, at least one of the first step structure and the second step structure comprises at least one pair of same-position steps, and the pair of same-position steps are arranged in the vertical plane in the stacking direction at intervals; and a plurality of conductive channels are formed on one side of the first step structure, the conductive channels are electrically connected with corresponding steps in the first step structure or the second step structure, and each pair of same-position steps are electrically connected with each other through the conductive channels.

Description

technical field [0001] The present application relates to the field of semiconductors, and more specifically, to a three-dimensional memory and a manufacturing method thereof. Background technique [0002] It is expected that the storage capacity of memory devices will gradually increase. However, some new problems may be encountered when increasing the storage capacity or storage density of a storage device, such as complex process, high manufacturing difficulty, and rising cost. [0003] As the number of stacked layers of the three-dimensional memory increases, in order to control the size of the three-dimensional memory and increase the storage density, the thickness of each layer can be selected to be thinned. However, when the thickness of the gate layer used for conduction becomes thinner, its resistance becomes larger, which in turn produces a larger resistance-capacitance delay (RC delay). In addition, when the thickness of the gate layer is controlled at a certain...

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Problems solved by technology

However, when the thickness of the gate layer used for conduction becomes thinner, its resistance will increase, which in turn will result in a larger resistance-capacitance delay (RC delay)

In addition, when the thickness of the gate layer is controlled at a certain thickness, the height of the entire stack structure becomes very high as the number of layers increases, and there will be more processing techniques such as deep etching or filling of such a tall stack structure. difficulty

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