Multi-core system resetting method, device and equipment and readable storage medium

Abstract

The invention provides a multi-core system reset method, device and equipment and a readable storage medium. The method comprises the steps of obtaining reset information of a target processor after a multi-core system executes bus reset; after it is judged that the target processor is reset successfully, whether all the remaining processors of the multi-core system are reset successfully or not is detected through the target processor; if yes, ending multi-core reset; and if it is detected that any processor is not reset successfully, controlling the register corresponding to the processor which is not reset successfully to reset again through the target processor until the rest processors of the multi-core system are all reset successfully, and ending multi-core reset. Reset detection and reset operation are carried out on the remaining processors through the target processor which is successfully reset, the situation that the processors are idle due to accidental failure of the processors available for the multi-core system can be avoided, reset is carried out in time to prevent application faults when any processor is abnormal, and the stability of the multi-core system is improved.

Description

technical field [0001] The present application relates to the technical field of chip design, and in particular, to a method, apparatus, device and readable storage medium for resetting a multi-core system. Background technique [0002] With the continuous development and improvement of science and technology, the functional requirements for CPUs are also getting higher and higher, and the functions of ordinary single-core systems have been unable to meet application requirements in some technical fields. Then came the multi-core system. With its advantages of execution efficiency, the multi-core system is gradually favored by the majority of users. With the birth of multi-core systems, there are also some technical issues between systems, especially how to coordinate and manage the reset of multiple cores. Only by managing the reset of the CPU can the system and other components be in a definite state. the initial state, and work normally from this initial state. [0003]...

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Problems solved by technology

[0003] In the process of conceiving and implementing this application, the inventor found that there are at least the following problems: At present, when the multi-core CPU chips are not all reset successfully, they will shield the cores that failed to reset, but the reset failure is not necessarily due to the failure of the core itself, and it may also be due to The instability of the clock leads to temporary inability to work, resulting in occasional reset failures; at the same time, because the existing multi-core system realizes the reset state of other cores by accessing a shared register during reset, when two or more than two When cores operate this shared register at the same time, bus errors are prone to occur; and the existing multi-core system cannot flexibly switch the reset state of other cores after a successful reset, resulting in the inability to generate software by itself when encountering external interference or man-made damage. Reset; in addition, the existing multi-core system reset technology cannot flexibly control which core has priority BOOT when the system starts for the first time, and the flexibility is low

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