Distributed bit line compensation digital-analog hybrid in-memory computing array

Abstract

The invention relates to the technical field of in-memory computing, in particular to a distributed bit line compensation digital-analog hybrid in-memory computing array, which comprises an in-memory computing module, an output module, a main control module and an input driving module, the main control module is respectively connected with the output module and the input driving module; the in-memory calculation module comprises four cluster in-memory calculation sub-modules, and each cluster in-memory calculation sub-module comprises four groups of in-memory calculation units; each group of in-memory calculation units comprises 32 rows * 8 columns of storage calculation circuits which are distributed in an array; the storage calculation circuits in each row are connected in parallel and then connected with the input driving module; each column of storage calculation circuits is connected in series, each column of storage calculation circuits is connected in series with a current mirror compensator, and each column of storage calculation circuits is connected with the output module through a coupling capacitor. According to the invention, the number of transistors is reduced, read-write interference is eliminated, and the problem of charging and accumulated voltage nonlinearity of a plurality of calculation units is corrected.

Description

technical field [0001] The invention relates to the technical field of in-memory computing, in particular to a distributed bit line compensation digital-analog hybrid in-memory computing array. Background technique [0002] In recent years, artificial intelligence (AI) has increasingly demanded energy-efficient computing systems, including edge intelligence and its applications, and von Neumann architectures are widely used to support various tasks using processing units (PEs), control units, and memory . Since the advent of artificial intelligence systems and deep neural networks (DNNs), von Neumann architectures have struggled to adapt to DNNs. DNNs in AI systems require massive parallel product (MAC) operations. During MAC operation, data transfer of a large number of weights and intermediate outputs is unavoidable between the processing unit (PE) and the memory, which leads to unavoidable power consumption and delay, which limits some AI applications, such as battery ...

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Problems solved by technology

[0003] The calculation method of traditional single-bit input multiplied by single-bit weight is inefficient, and a single calculation unit consumes a large number of transistors, and because the weight is connected to the source and drain of the calculation transistor, it will cause damage to the bit line voltage when the calculation process is too large. Not only that, when the same column contains multiple calculation units for calculation, if the number of effective calculation units is too large, the increase of the coupling capacitor voltage and the number of effective calculation units will have a nonlinear relationship, which will cause the calculation results to fail. Accurately quantified; secondly, the traditional arrangement of large-array storage and calculation units will cause excessive load on the word line and bit line, which will cause the pulse signal on the word line to attenuate significantly. If the word line pulse width becomes narrow after the attenuation After that, the charging time of the effective calculation unit to the coupling capacitor will be shortened, which will also affect the accuracy of the calculation result

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