Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the steps that a substrate is provided, the substrate comprises a first region, and a first fin part is arranged on the first region; forming an initial isolation layer on the substrate; forming a first gate structure on the substrate; forming a first source-drain opening in the first fin part at two sides of the first gate structure; etching back a part of the initial isolation layer to form an isolation layer; and forming a first source-drain doping layer in the first source-drain opening, wherein the first source-drain doping layer is internally provided with first source-drain ions. The isolation layer is formed by etching back part of the initial isolation layer, so that more first source-drain openings are exposed out of the isolation layer, the limitation of the isolation layer on a first source-drain doping layer formed by epitaxial growth is further reduced, and the volume of the first source-drain doping layer is increased. When the volume of the first source-drain doping layer is increased, the dosage of the first source-drain ions doped in the first source-drain doping layer is correspondingly increased, so that the current between the first source-drain doping layer is improved, and the performance of the finally formed semiconductor structure is improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background technique [0002] With the improvement of the integration level of semiconductor devices, the critical dimension of transistors is continuously reduced, and the reduction of the critical dimension means that a larger number of transistors can be arranged on a chip, thereby improving the performance of the device. However, as device areas continue to shrink, problems also arise. With the sharp reduction of the size of the transistor, the thickness of the gate dielectric layer and the operating voltage cannot be changed accordingly, which makes it more difficult to suppress the short-channel effect and increases the channel leakage current of the transistor. [0003] The MOS tube shrinks and the gate becomes shorter, so that the current channel under the gate also becomes shorter. When the...

AI Technical Summary

Problems solved by technology

However, when the first width dimension of the gate structure is increased, other problems will also occur, so that the performance of the final semiconductor structure is reduced.

Therefore, the performance of semiconductor structures formed in the prior art still needs to be improved

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