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Quadrature clock skew calibration circuit

A technology for calibrating circuits and clock skew, applied to electrical components, generating electrical pulses, pulse technology, etc., can solve problems such as power consumption and jitter

Pending Publication Date: 2022-05-27
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, adjustable delay stages add delay cells to the circuit, which consume additional power and cause jitter
Additionally, calibration resolution is limited by the delay of each delay stage

Method used

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  • Quadrature clock skew calibration circuit
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  • Quadrature clock skew calibration circuit

Examples

Experimental program
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Embodiment Construction

[0020] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, some but not all embodiments. Indeed, these concepts may be embodied in many different forms and should not be construed as limiting herein. Rather, these descriptions are provided so that this disclosure will satisfy applicable requirements.

[0021] figure 1 is a block diagram of a quadrature clock skew calibration circuit 100 according to an exemplary embodiment. Quadrature clock skew calibration circuit 100 is configured to calibrate or adjust the skew between in-phase (I) and quadrature (Q) clock signals. Circuit 100 includes an I-Q clock generator 104 having an input 108 coupled to receive a first clock signal. The I-Q clock generator 104 generates an I clock signal and a Q clock signal in response to the first clock signal. Circuit 100 also includes an I-Q skew sensor 112 having a first input 116 coupled to receive an I clock signal and a s...

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PUM

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Abstract

A quadrature clock skew calibration circuit (100) includes an I-Q clock generator (104) having an input coupled to receive a first clock signal. An I-Q clock generator generates an in-phase (I) clock signal and a quadrature (Q) clock signal. A quadrature clock skew calibration circuit (100) includes an I-Q skew sensor (112) having a first input coupled to receive an I clock signal and a second input coupled to receive a Q clock signal. An I-Q skew sensor (112) generates an I-Q skew signal in response to a skew between the I and Q clock signals. A quadrature clock skew calibration circuit (100) includes a control circuit (124) having a first input coupled to receive an I-Q skew signal and a second input coupled to receive a second clock signal. A control circuit (124) changes a duty cycle of the first clock signal in response to the I-Q skew signal and the second clock signal.

Description

technical field [0001] The present disclosure generally relates to quadrature clock skew calibration circuits. Background technique [0002] In high-speed asynchronous serial data links, the phase difference between the clock and data signals often becomes prominent during propagation. This is undesirable for many applications that require the clock and data signals to be in phase for proper operation. Clock and data recovery (CDR) systems can be used to accurately recover information from high-speed serial transmissions. In a half-rate CDR system, CDR locking requires precise quadrature clocks that output an in-phase (I) clock signal and a quadrature (Q) clock signal. If the phases between the I clock signal and the Q clock signal are not in quadrature, the CDR system will not be able to lock close to the center of the incoming data, resulting in an error in the final CDR lock point, resulting in bit errors. Therefore, the skew between the I clock signal and the Q clock ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/05H03K19/003
CPCH03K5/05H03K5/15006H04L7/033H03K5/1565H03K23/44H04L7/0037H04L7/0087H03K3/037H03K3/017
Inventor R·里贝罗
Owner TEXAS INSTR INC