Integrated circuit and clock signal distribution method thereof

Abstract

The invention provides an integrated circuit and a clock signal distribution method thereof. The integrated circuit comprises a clock source configured to generate a clock signal of the integrated circuit; at least two function modules; the at least two clock generators correspond to the functional modules and are configured to determine initial phases of the functional modules; and according to the clock signal of the integrated circuit and the initial phase, generating a clock signal of the functional module, so that the clock signals of the functional modules are kept synchronous, wherein the initial phase is determined according to the transmission distance of a clock signal of the integrated circuit transmitted from the clock source to the functional module and the load of the functional module.

Description

technical field [0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to an integrated circuit and a clock signal distribution method thereof. Background technique [0002] The clock is the basic functional unit of the integrated circuit, which is equivalent to the heart of the IC and is used to drive the digital circuit. With the advancement of semiconductor technology, the feature size of the chip manufacturing process has been reduced year by year, the number of transistors integrated per unit area has increased exponentially, and more and more circuits are integrated into a single wafer, and the scale has exceeded 10 billion transistors. Behind such a huge number , the clock distribution brings many problems, such as setup time and hold time violations, exponential increase in the area of ​​the auxiliary circuit for clock distribution, and extra clock power consumption. SUMMARY OF THE INVENTION [0003] In view of this...

AI Technical Summary

Problems solved by technology

With the advancement of semiconductor technology, the feature size of the chip manufacturing process has been reduced year by year, the number of transistors integrated per unit area has increased exponentially, and more and more circuits are integrated in a single wafer, and the scale has exceeded tens of billions of transistors. , clock distribution brings many problems, such as setup time and hold time violation, clock distribution auxiliary circuit area exponential increase, additional clock power consumption, etc.

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