Three-dimensional memory and manufacturing method thereof, storage system and electronic equipment
A memory, three-dimensional technology, applied in circuits, electrical components, semiconductor devices, etc., can solve the problems affecting the performance of 3DNAND and the filling of gate line materials, and achieve the effect of improving filling filling and improving structural stability.
Pending Publication Date: 2022-06-24
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
However, in the above manufacturing process, when depositing the gate line material in the gap, there is a problem that the gate line material is not fully filled, which affects the performance of 3D NAND
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[0052] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided by the present disclosure fall within the protection scope of the present disclosure.
[0053] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "horizontal", "bottom", "inner", "outer" and the like is based on the attached The orientation or positional relationship shown in the figures is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the indicated device or element must have a ...
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The invention provides a three-dimensional memory and a manufacturing method thereof, a memory system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem that grid line materials are not filled compactly. The three-dimensional memory comprises a plurality of dielectric layers, a plurality of channel structures, a plurality of contact structures, a first grid line isolation structure, a middle isolation structure and a second grid line isolation structure, the intermediate isolation structure extends from the array region to the transition region, and the first gate line isolation structure and the second gate line isolation structure extend from the array region to the contact region. The dielectric layer comprises a first sub-grid line, a second sub-grid line and a connecting part. And the connecting part exceeds the middle isolation structure in the first direction and is in contact with the first sub-grid line and the second sub-grid line. A first gap is formed in the middle of one end, close to the contact area, of the first sub-grid line, a second gap is formed in the middle of one end, close to the contact area, of the second sub-grid line, and in the second direction, the connecting part does not exceed the edges, close to each other, of the first gap and the second gap.
Description
technical field [0001] The present disclosure relates to the technical field of semiconductor chips, and in particular, to a three-dimensional memory and a manufacturing method, a storage system, and an electronic device. Background technique [0002] As the feature size of the memory cell approaches the lower process limit, planar processes and fabrication techniques become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach the upper limit. [0003] To overcome the limitations imposed by 2D or planar NAND flash memory, the industry has developed memories with a three-dimensional structure (3D NAND), which increases storage density by arranging memory cells three-dimensionally on a substrate. [0004] In the process of making 3D NAND, a gap can be formed by removing part of the material layer. The gate line material in the gap is then deposited to form gate lines in 3D NAND. However, in the above manufacturing process, when th...
Claims
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IPC IPC(8): H01L27/1157H01L27/11575H01L27/11582H01L27/11524H01L27/11548H01L27/11556H10B43/35H10B41/27H10B41/35H10B41/50H10B43/27H10B43/50
CPCH10B41/35H10B41/50H10B41/27H10B43/35H10B43/50H10B43/27
Inventor 王迪张中
Owner YANGTZE MEMORY TECH CO LTD