Test system and method for detecting latch-up effect of chip
A latch-up effect and test system technology, applied in the field of test systems for detecting chip latch-up effect, can solve the problems of high cost, long test solution time, high cost, etc., and achieve the effect of easy implementation
Pending Publication Date: 2022-07-01
BEIJING TONGFANG MICROELECTRONICS
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Problems solved by technology
[0004] As can be seen from the current flow chart of the latch-up effect test solution, the entire test takes 5 days. If the third-party testing agency entrusts more tasks, the test time will be extended, and the test may not be completed in 10 days.
In addition to the longer time, scripts need to be written before each test, and the more detailed the test, the more complex the script, the longer the time, and the resulting costs are extremely expensive
As a result, existing latch-up testing solutions are time-consuming, cumbersome and expensive
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[0033] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
[0034] In order to make the above objects, features and advantages of the present invention more clearly understood, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.
[0035] see figure 1 , which is a block diagram of a testing system for detecting the latch-up effect of a chip implemented by the present invention. In this specific embodiment, the te...
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The invention provides a test system and method for detecting the latch-up effect of a chip, the test system comprises a stabilized voltage supply, a PCB, a to-be-tested chip and a multimeter, the PCB comprises a stabilized voltage supply voltage device, an electric signal pulse generation device, a to-be-tested equipment socket and a trigger switch; when the latch-up effect test of the chip to be tested is carried out, the universal meter is used for measuring the current value of the power supply pin of the chip to be tested and judging whether the triggered pulse voltage signal causes the latch-up effect or not, so that the latch-up effect test of the chip to be tested has the characteristics of rapidness, easiness in implementation, simplified test process and low cost.
Description
technical field [0001] The invention relates to the technical field of integrated circuit chip reliability testing, in particular to a testing system and a method for detecting chip latch-up effect. Background technique [0002] With the development of electronic technology, the integration level of electronic circuits becomes higher and higher, and related voltage transients may cause failure of semiconductor devices, that is, latch-up. The latch-up effect can cause the device to form a short circuit between the power supply and the ground, resulting in high current, EOS and device damage, which is a potentially serious problem that affects the reliability of the device. Therefore, evaluating the anti-latch capability of the chip through the latch-up test is of great significance to ensure the quality of the chip. Aiming at the problems existing in the existing testing process, this patent proposes a scheme for self-examination testing. [0003] The existing method for te...
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Login to View More IPC IPC(8): G01R31/28
CPCG01R31/2836
Inventor 刘静陈凝郭耀华欧阳睿赵旭
Owner BEIJING TONGFANG MICROELECTRONICS