System for realizing asymmetric algorithm multi-core parallel architecture by using single instruction memory through multiple lightweight processors

Abstract

The invention discloses a system for realizing an asymmetric algorithm multi-core parallel architecture by multiple lightweight processors by using a single instruction memory. The system comprises an AXI bus, an interface terminal, an ultra-high-speed interface, a high-speed interface, a main control processor, an instruction register, an asymmetric key memory and a plurality of lightweight processors, each lightweight processor is connected with an asymmetric algorithm core and an asymmetric interface memory, and each lightweight processor is connected with the instruction register and the asymmetric key memory; and the asymmetric key memory, the asymmetric interface memory, the interface terminal, the ultra-high-speed interface, the high-speed interface and the main control processor are all connected with the AXI bus. The method has the advantages that the chip area of the asymmetric algorithm is reduced by using one instruction memory to provide instruction reading for a plurality of light processors and one asymmetric key memory to provide asymmetric keys for a plurality of light processors, so that the cost is reduced, and the chip does not generate excessive heat during working.

Description

technical field [0001] The invention relates to the technical field of digital IC circuit design, in particular to a system in which multiple lightweight processors use a single instruction memory to implement an asymmetric algorithm multi-core parallel architecture. Background technique [0002] Existing security chips using asymmetric algorithms are mostly used in eSIM cards, bank cards and application terminals, which require high area and power consumption, which makes the performance of asymmetric algorithms not high enough. In order to achieve high performance, most firmware services are implemented in hardware. Solution, but limited by power consumption and low main frequency, the performance is not ideal. The security chip of the asymmetric algorithm used on the server side is relatively insensitive to area and power consumption. Some of the existing technologies use mature solutions on eSIM cards, bank cards and application terminals to realize multi-core technology...

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a system in which many lightweight processors use a single instruction memory to implement an asymmetric algorithm multi-core parallel architecture, thereby solving the aforementioned problems in the prior art

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