Verification method combining scoreboard and assertion check

Abstract

The invention discloses a verification method combining a scoreboard and assertion check, which comprises the following steps of: declaring a uvevent event in the scoreboard for controlling an enabling switch variable of assertion; the method comprises the following steps of: instantiating a uvevent event in a build phase in a phase mechanism of a UVM (Universal Virtual Machine), and transmitting the instantiated uvevent event into a configuration database of the UVM; all assertions used for checking are packaged into a package file, and the on-off state of the assertions can be controlled through a disable iff () keyword; creating an assertion configuration object which is generated by the uvmoobject in the package file, and creating an assertion configuration object which is generated by the uvmoobject in the package file; creating a verification platform, and importing a package file into a top layer module of the verification platform, so that a verification environment of the verification platform can use the packaged assertion check and assertion configuration object; and the check commands are sequentially executed in the program control block according to the execution sequence, and the assertion check result is obtained, so that further time sequence and protocol signal level check of the problems tracked in the scoreboard is realized. The verification work efficiency and the verification quality can be improved.

Description

technical field [0001] The invention relates to the technical field of chip verification, in particular to a verification method combining a scoreboard and an assertion check. Background technique [0002] Usually, we use assertion (systemVerilog assertion) and scoreboard (scoreboard) to check the function of RTL design (DUT) to ensure that the function of RTL design meets the description requirements of the design manual. [0003] (1) Scoreboard verification method [0004] like figure 1 As shown, the scoreboard usually consists of two parts, the reference model (predictor) and the comparator (evaluator). Usually, in order to check the correctness of the DUT function, we need to write a reference model (predictor), and then send the same excitation to the reference model and DUT, and then after each operation, send the operation result to the comparator (evaluator) for comparison, through the comparison The correctness of the DUT function can be judged by checking whethe...

AI Technical Summary

Problems solved by technology

[0010] The scoreboard in the existing scheme ( figure 2 in scoreboard) and assertions ( figure 2 Assertion) checks exist at the same time. Since concurrent assertions are usually checked based on clock changes, concurrent assertions will be checked every clock cycle. However, there are a large number of situations where assertion checks are not required, because the scoreboard does not The problem of comparing errors is not reported every clock cycle, so doing concurrent assertion checks every clock cycle will reduce simulation performance and prolong simulation time, thereby reducing the productivity of verification developers

[0011] The above defects are often due to the fact that the two inspection methods operate independently of each other, that is, they lack correlation with each other

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