Semiconductor structure

Abstract

A semiconductor structure includes a substrate, and first and second SRAM cells. Each first SRAM unit comprises two first p type FinFETs (FinFET) and four first n type FinFETs (FinFET); each of the first p-type and first n-type FinFETs includes a channel in a single semiconductor fin. The first SRAM cell has a first X pitch and a first Y pitch. And each second SRAM unit comprises two second p type FinFETs (FinFET) and four second n type FinFETs (FinFET). Each of the second p-type FinFETs includes a channel in a single semiconductor fin. Each of the second n-type FinFETs includes a channel in a plurality of semiconductor fins. The second SRAM cell has a second X pitch and a second Y pitch. The source / drain region of the first p-type FinFET has a higher boron dopant concentration than the source / drain region of the second p-type FinFET. A ratio of the second X-pitch to the first X-pitch is in a range of 1.1 to 1.5.

Description

technical field [0001] The present invention relates to semiconductor structures and processes thereof, and in particular to high-density implementations of fin field effect (FinFET) transistors or gate-all-around (GAA) transistors; HD) memory cells and integrated circuits (ICs) of high-current (HC) (or high-speed (HS)) memory cells. Background technique [0002] The electronics industry faces an increasing demand for smaller and faster electronic devices that simultaneously need to support a large number of increasingly complex and sophisticated functions. To meet this need, a continuing trend in the semiconductor industry is to manufacture integrated circuits (ICs) that are low cost, high performance, and low power. To date, most of these goals have been achieved by reducing the size of semiconductor ICs (eg, IC minimum feature size), thereby improving process efficiency and reducing associated costs. However, such size reductions also increase the complexity of the semi...

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Problems solved by technology

However, this type of scaling also increases the complexity of the semiconductor manufacturing process

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