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Thin film transistor, memory, manufacturing method and electronic equipment

A technology of thin film transistor and memory, applied in the fields of electronic equipment, thin film transistor, memory and manufacturing method, can solve the problems of low area utilization rate, large size of thin film transistor 10, unfavorable wiring and the like

Pending Publication Date: 2022-07-26
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Since the semiconductor layer 102 of the existing thin film transistor 10 is spread along a plane parallel to the gate 106, and the source electrode 103 and the drain electrode 104 are located on the same layer, the size of the thin film transistor 10 is large and the area utilization rate is low.
In addit

Method used

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  • Thin film transistor, memory, manufacturing method and electronic equipment
  • Thin film transistor, memory, manufacturing method and electronic equipment
  • Thin film transistor, memory, manufacturing method and electronic equipment

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0268] For example make Figure 8a The thin film transistor 10 shown specifically includes the following steps:

[0269] S100, such as Figure 19 As shown, a stacked first conductive film 1090 , a first dielectric film 1130 and a second conductive film 1080 are sequentially formed on the substrate 101 .

[0270] Here, the first conductive film 1090 , the first dielectric film 1130 and the second conductive film 1080 may be sequentially formed by chemical vapor deposition, physical vapor deposition, sputtering, electroplating and other methods.

[0271] S101, such as Figure 19 As shown, the first conductive film 1090, the first dielectric film 1130 and the second conductive film 1080 are patterned to form the first electrode 109, the first dielectric layer 113 and the second electrode 108 stacked in sequence; wherein, the first electrode 109 , the first dielectric layer 113 and the second pole 108 form a groove structure.

[0272] Here, the first conductive film 1090, the ...

Embodiment 2

[0282] For example make Figure 9 The thin film transistor 10 shown specifically includes the following steps:

[0283] S110, such as Figure 20As shown, a stacked first conductive film 1090 , a first dielectric film 1130 and a second conductive film 1080 are sequentially formed on the substrate 101 .

[0284] Here, for the specific implementation process of this step S110, reference may be made to the above-mentioned step S100, which will not be repeated here.

[0285] S111, such as Figure 20 As shown, the first conductive film 1090, the first dielectric film 1130 and the second conductive film 1080 are patterned to form the first electrode 109, the first dielectric layer 113 and the second electrode 108 stacked in sequence; wherein, the first electrode 109 , the first dielectric layer 113 and the second pole 108 form a groove structure.

[0286] Here, for the specific implementation process of this step S111, reference may be made to the foregoing step S101, which will ...

Embodiment 3

[0294] For example make Figure 10 The thin film transistor 10 shown specifically includes the following steps:

[0295] S120, such as Figure 21 As shown, a stacked first conductive film 1090 , a first dielectric film 1130 and a second conductive film 1080 are sequentially formed on the substrate 101 .

[0296] Here, for the specific implementation process of this step S120, reference may be made to the above-mentioned step S100, which will not be repeated here.

[0297] S121, such as Figure 21 As shown, the first conductive film 1090, the first dielectric film 1130 and the second conductive film 1080 are patterned to form the first electrode 109, the first dielectric layer 113 and the second electrode 108 stacked in sequence; wherein, the first electrode 109 , the first dielectric layer 113 and the second pole 108 form a groove structure.

[0298] Here, for the specific implementation process of this step S121, reference may be made to the foregoing step S101, which wil...

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PUM

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Abstract

The embodiment of the invention provides a thin film transistor, a memory, a manufacturing method and electronic equipment, relates to the technical field of memories, and can reduce the size of the thin film transistor, improve the area utilization rate and reduce the wiring difficulty. The thin film transistor comprises a grid electrode, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer and a semiconductor layer. Wherein the grid electrode comprises a grid substrate located at the top and a grid electrode column extending from the grid substrate to the bottom; the first pole is located at the bottom; the second electrode is located between the first electrode and the gate substrate; the first dielectric layer is arranged between the second pole and the first pole, and the first dielectric layer is used for separating the first pole from the second pole; the second dielectric layer covers the surface of the gate substrate and the surface of the gate column; the semiconductor layer is arranged along the side face of the gate column, and the second dielectric layer separates the semiconductor layer from the gate. The first pole and the second pole are electrically connected to the semiconductor layer, respectively.

Description

technical field [0001] The present application relates to the technical field of memory, and in particular, to a thin film transistor, a memory, a manufacturing method, and an electronic device. Background technique [0002] Since thin film transistors (TFTs) have the advantages of low leakage current, low growth temperature, and high mobility, thin film transistors have been widely used in various devices such as memories. [0003] The structure of the existing thin film transistor is such as figure 1 As shown, the thin film transistor 10 includes a semiconductor layer (also referred to as an active layer) 102 disposed on a substrate 101, a source electrode 103 and a drain electrode 104 disposed on the semiconductor layer 102 and in contact with the semiconductor layer 102, The gate insulating layer 105 on the semiconductor layer 102 and the gate electrode 106 provided on the gate insulating layer 105 . [0004] Since the semiconductor layer 102 of the existing thin film ...

Claims

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Application Information

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IPC IPC(8): H01L29/786H01L29/423H01L29/06G11C16/08G11C16/24
CPCH01L29/786H01L29/42356H01L29/42364H01L29/0603H01L29/0684G11C16/08G11C16/24H01L29/423H01L29/06G11C11/401H01L29/78642H01L29/42384H01L29/78696H01L29/78645H10B41/70H10B41/27H01L29/6675H10B12/00
Inventor 景蔚亮黄凯亮冯君校王正波
Owner HUAWEI TECH CO LTD