Layout construction method

Abstract

The invention discloses a layout construction method, which is used for simulating a use environment of a standard cell library unit, and comprises the following steps: determining a substrate potential, and connecting a substrate with a set potential power supply by the standard cell library unit through a substrate connecting unit; simulating an active area environment, and adding active areas without electric characteristics on the upper, lower, left and right sides of the standard cell library unit; simulating an injection layer environment, wherein the width of the injection layer is greater than that of the injection layer of the standard cell library unit; simulating a grid environment, arranging invalid grids in the up-down and left-right directions of the effective grids of the standard cell library, and simulating an environment after up-down and left-right splicing of the cell library; simulating a first-layer metal environment, namely arranging vertically suspended first-layer metal wires on the left and right sides of the standard cell library unit to simulate a metal wire environment; and simulating a second-layer metal environment, namely placing vertically suspended second-layer metal wires on the left and right sides of the standard cell library unit to simulate a metal wire environment. According to the invention, the accuracy of the standard cell library unit in the characterization process can be improved.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a layout construction method. Background technique [0002] In the field of semiconductor integrated circuit manufacturing, each process requires a corresponding set of standard cell libraries. Before tape-out, the standard cells in the standard cell library need to be used for automatic logic synthesis and layout layout. The advantage of the design method based on the standard cell library is that under a certain type of process node, the standard cell library only needs to be designed once and successfully verified, and can be reused in subsequent designs, which greatly improves the Design efficiency, amortized design cost. [0003] refer to figure 1 As shown, in the existing characterization process, the standard cell library unit is connected to the substrate through the substrate connection unit, and the substrate is connected to the set potential power supply. Then, th...

AI Technical Summary

Problems solved by technology

The characterization process does not consider the second-order effect of the standard unit in the actual working environment and the influence of parasitic resistance and capacitance on it, which eventually leads to deviations in timing information and power consumption information, resulting in inaccurate comprehensive results and even functional failures.

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