Accelerator

Abstract

The invention relates to an accelerator which comprises a write channel and a read channel, and the write channel comprises a logic circuit and a plurality of caches; the logic circuit obtains an address index and an L2P table entry from the write command; determining one or more memory addresses corresponding to the L2P table entry and the position of the first bit of the valid data in the memory according to the address index and the valid data bit of the L2P table entry; the read channel responds to valid data byte alignment and a first bit is not located at an initial position of a corresponding storage unit in the memory or non-byte alignment, one or more read commands are generated according to one or more memory addresses, and the one or more read commands are sent to the memory; in response to received response data fed back by the memory based on each read command, combining the valid data with partial data in the response data according to the position of the first bit to obtain first data; and generating second data according to the protocol information and the first data, and sending the second data to the memory.

Description

technical field [0001] This application relates generally to the field of memory. More specifically, the present application relates to an accelerator. Background technique [0002] figure 1 A block diagram of a solid-state storage device is shown. The solid state storage device 102 is coupled to the host for providing storage capabilities for the host. The host and the solid-state storage device 102 can be coupled in various ways, including but not limited to, for example, SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment), SCSI (Small Computer System Interface, Small Computer System Interface) , SAS (Serial Attached SCSI, Serial Attached SCSI), IDE (Integrated Drive Electronics, Integrated Drive Electronics), USB (Universal Serial Bus, Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe, high-speed peripheral component interconnection), NVMe (NVM Express, high-speed non-volatile storage), Ethernet, Fibre Channel...

AI Technical Summary

Problems solved by technology

However, limited by the memory chip and CPU addressing mode, the CPU addressing channel takes an integer multiple of 32 bits or bytes as the data width of one address, and the memory chip usually uses an integer multiple of bytes as the data width

Thus if the entry size of the L2P table is, for example, 30 bits, although the overall size of the L2P table is reduced, entries crossing byte boundaries require, for example, 2 or more bus accesses or memory accesses to be loaded into the CPU, thereby significantly Increased loading time of L2P table entries, limiting storage device performance

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