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Burst mode type semiconductor memory device

A storage device and pulse train technology, applied in pulse technology, information storage, static memory, etc., can solve problems such as increased power consumption

Inactive Publication Date: 2004-05-19
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] Even in the fourth prior art semiconductor memory device, power consumption increases
Furthermore, the power consumption increases because the device includes a comparator to find out if any change has occurred in the stored information in order to suspend the supply of the clock signal

Method used

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  • Burst mode type semiconductor memory device
  • Burst mode type semiconductor memory device
  • Burst mode type semiconductor memory device

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Embodiment Construction

[0034] Before describing the preferred embodiment of the present invention, a prior art semiconductor memory device will be described with reference to FIGS. 1, 2, 3A, 3B, 4A, 4B, 5, 6, and 7.

[0035] FIG. 1 illustrates a first prior art semiconductor memory device, and reference numeral 101 denotes a memory cell array. In addition, an address buffer / decoder 1021 is provided. Furthermore, an input-output buffer 1031 , an input-output memory circuit 1032 , an input-output buffer 1041 and an input-output memory circuit 1042 are provided. Furthermore, buffers 1051 and 1061 for control signals and memory circuits 1052, 1062 for control signals are also provided.

[0036] The clock signal CK is supplied from the pad 1701 to the memory circuits 1052 and 1062 through the inverters 1072 and 1073 . Clock signal CK is supplied from pad 1701 to memory circuits 1042 (1032) and 1022 through inverters 1074 (1074') and 1075 (1075').

[0037] A memory circuit and a buffer of the apparatus...

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Abstract

In a semiconductor memory device having a burst function, a memory circuit inputs and outputs information corresponding to an external input signal in synchronization with an internal clock signal. A burst operation control circuit receives an external reference clock signal and an enable signal for switching a burst operation mode and a stand-by mode, so as to suspend supplying of the external input signal in the burst operation mode and suspend generation of the first internal clock signal in the stand-by mode.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having burst characteristics and suitable for operation with low power consumption. Background technique [0002] In recent years, pipelined burst static random access memory (PBSRAM) devices having a burst-like feature have played an important role in rapidly improving the performance of personal computers, where they are used as secondary cache memories. About 100% of currently used notebook type personal computers, including home personal computers, are provided with one or several PBSRAM devices. The PBSRAM device is required to operate to perform data processing at high speed and to have low power consumption especially when it is used for a notebook type personal computer. The term "burst-like feature" refers to the feature of performing a burst-like operation of fetching an external start address, then internally and automatic...

Claims

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Application Information

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IPC IPC(8): G11C11/413G11C7/10H03K19/00
CPCG11C7/1018G11C7/1039G11C7/00
Inventor 川口康成
Owner RENESAS ELECTRONICS CORP