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Electronic device and and its mfg. method

A manufacturing method and technology of electronic devices, which are applied in the fields of electric solid-state devices, semiconductor/solid-state device manufacturing, electrical components, etc., and can solve problems such as low effective utilization rate and broken substrate 11

Inactive Publication Date: 2004-05-26
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is, the substrate 11 whose mechanical strength has been reduced after thinning needs to be transported to the mask forming device and etching device, and the substrate 11 is likely to be broken during the transport process.
Therefore, the conventional electronic device manufacturing method has the problem of low effective utilization rate.

Method used

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  • Electronic device and and its mfg. method
  • Electronic device and and its mfg. method
  • Electronic device and and its mfg. method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0085] Hereinafter, a method for manufacturing an electronic device according to Embodiment 1 of the present invention will be described with reference to FIGS. 1( a ) to ( f ).

[0086] First, as shown in FIG. 1( a ), on the front surface of a GaAs substrate 101 with a thickness of 150 μm, selective arsenic ion implantation is performed using a protective mask, and then activation heat treatment is performed to form an active layer 102 with a thickness of 0.2 μm. Afterwards, on the active layer 102, a first protective mask having openings in the region where the source electrode and the drain electrode are formed is formed, and then an alloy film of gold and germanium and a gold film are sequentially deposited on the first protective mask. After the first protective mask is removed, the source electrode 103 and the drain electrode 104 having ohmic contact with the active layer 102 are formed. In addition, on the active layer 102, a second protective mask having an opening in ...

Embodiment 2

[0095] Hereinafter, a method of manufacturing an electronic device according to Embodiment 2 of the present invention will be described with reference to FIGS. 2( a ) to ( f ).

[0096] First, as shown in FIG. 2( a ), selective arsenic ion implantation is performed on the front surface of a GaAs substrate 201 with a thickness of 150 μm, followed by activation heat treatment to form an active layer 202 with a thickness of 0.2 μm. Thereafter, as in the first embodiment, the source electrode 203 and the drain electrode 204 having ohmic contact with the active layer 202 are formed, and the gate electrode 205 is formed with a Schottky contact with the active layer 202 . Thus, a FET is formed by the active layer 202, the source electrode 203, the drain electrode 204, and the gate electrode 205.

[0097] In addition, the source electrode 203 in Embodiment 2 is different from the source electrode 103 in Embodiment 1. It has a certain extension on the side opposite to the gate electrod...

Embodiment 3

[0107] Hereinafter, a method of manufacturing an electronic device according to Embodiment 3 of the present invention will be described with reference to FIGS. 3( a ) to ( f ).

[0108] First, as shown in FIG. 3( a ), selective arsenic ion implantation is performed on the front surface of a GaAs substrate 301 with a thickness of 150 μm, followed by activation heat treatment to form an active layer 302 with a thickness of 0.2 μm. Thereafter, as in the first embodiment, the source electrode 303 and the drain electrode 304 having ohmic contact with the active layer 302 are formed, and the gate electrode 305 having a Schottky contact with the active layer 302 is formed. Thus, a FET is formed by the active layer 302, the source electrode 303, the drain electrode 304, and the gate electrode 305.

[0109] In addition, in the third embodiment, the source electrode 303 has a certain extension on the side opposite to the gate electrode 305 as in the second embodiment, and has an opening...

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Abstract

A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed.

Description

technical field [0001] The invention relates to an electronic device used in the field of information and communication such as a mobile communication device and a manufacturing method thereof. Background technique [0002] In recent years, the demand for mobile communication devices such as mobile phones and personal handyphone systems (PHS) has rapidly expanded, and correspondingly, frequencies used by mobile communication devices have expanded from the MHz band to the GHz band. Gallium arsenide field effect transistor (GaAsFET) with high gain, low distortion and low current in the high frequency band is widely used in the frequency conversion circuit or signal amplification circuit of the signal receiving part or the transmitting signal part of these mobile communication devices. application. [0003] GaAsFET is formed by first forming GaAs on a semi-insulating substrate, and then cutting the chip by slicing during assembly. After the cut chips are assembled on the wiri...

Claims

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Application Information

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IPC IPC(8): H01L29/41H01L21/3205H01L21/338H01L21/66H01L21/768H01L23/48H01L23/52H01L29/812
CPCH01L21/76898H01L2924/0002H01L23/481H01L2924/3011H01L2924/00H01L21/8252
Inventor 古川秀利野间淳史田中毅石田秀俊上田大助
Owner PANASONIC CORP