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Quasi-synchronous multistage synchronous event device

A synchronous event, quasi-synchronous technology, applied in the direction of generating/distributing signals, etc., can solve problems such as inability to guarantee clock uncertainty

Inactive Publication Date: 2005-10-05
SILICON INTEGRATED SYSTEMS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In a generally known electronic system, such as a known computer system, there may generally be several clock sources. For example, a personal computer system (PC) generally has three different clock sources of CPU, memory and I / O devices. Therefore, it is necessary to synchronize the data transmission control signals of these asynchronous digital circuits with different clocks using a synchronizer, but even so, there are still some clock uncertainties that cannot be guaranteed for data and control signal transmission in the aforementioned asynchronous Disadvantages between the generating end and the receiving end of digital circuits

Method used

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Embodiment Construction

[0074] Please refer to figure 1 , figure 1 The function of the synchronizer 10 is to synchronously convert the D2 signal from the PDU_CLK time domain (clockdomain) to the CSM_CLK time domain, and at the same time generate the Q1 signal output to the CSM_CLK time domain, in other words, knock out the synchronously converted The signal Q2 is output, and the Q2 signal is safely sampled by the D-F / F clock component 12 . please refer again figure 2 ,Should figure 2 It shows the basic circuit structure of a standard synchronizer 10, and the desired synchronization signal D1 is knocked out at the PDU-CLK clock of the J-K F / F clock component 20, and simultaneously outputs a clock synchronous with the PDU-CLK The S1 signal, and then the S1 signal will be sampled by the CSM_CLK in the D-F / F clock component 21 to generate an output signal S2, and then the S2 signal will be sampled by the CSM_CLK in the D-F / F clock component 22 to generate an output signal S3. Finally, the output ...

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Abstract

The present invention provides one quasi-synchronous multistage synchronous event device, and is especially one for improving clock delay and phase error produced in asynchronous digital circuits in the generating end and the receiving end of computer system by means of one quasi-synchronous multistage synchronizer and one control circuit with phase locking loop.

Description

technical field [0001] The present invention is a quasi-synchronous multi-stage synchronous event device used in computer electronic systems, especially a multi-stage synchronous event routing (SYNC event) by means of a quasi-synchronous multi-stage synchronizer (Quasi-Synchronous Multi-Stage Synchronizer). routing) and a Phase Lock Loop (PLL) Control Circuit (Phase Lock Loop (PLL) Control Circuit) phase control to improve the production-end (producing-end) and receiving-end (consuming-end) in the computer (PC) system The clock delay and phase error generated between the asynchronous digital circuits can further improve the performance and reliability of the electronic system of the computer. Background technique [0002] In a generally known electronic system, such as a known computer system, there may generally be several clock sources. For example, a personal computer system (PC) generally has three different clock sources of CPU, memory and I / O devic...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/12
Inventor 苏仁斌赵梓翔陈灿辉
Owner SILICON INTEGRATED SYSTEMS