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Electrostatic discharge protector

An electrostatic discharge protection and device technology, applied in the field of transistors

Inactive Publication Date: 2002-11-13
WINBOND ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, to use self-aligned silicide to increase the operating speed of the device, it is necessary to maintain sufficient ESD protection circuits.

Method used

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Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0064] like Figure 2A to Figure 2C Shown is a schematic plan view of an ESD protection device of the first embodiment of the present invention; Figure 3A to Figure 3C shown, respectively, corresponding to Figure 2A to Figure 2C Schematic cross-sectional view of the ESD protection device in .

[0065] Please also refer to Figure 2A and Figure 3A , the manufacturing method of the ESD device, firstly, an oxide layer 100 and a polysilicon layer 102 are sequentially formed on the P-type silicon substrate 104 . Then please refer to Figure 2B and Figure 3B , performing a lithography process to form polysilicon islands 106 , 108 , 110 , 112 and polysilicon gates 114 , 116 . Then please refer to Figure 2C and Figure 3C , perform an ion implantation step 118 to form an N+ doped region 120 , wherein the N+ doped region 120 includes an N+ drain doped region 122 and an N+ source doped region 124 .

[0066] like Figure 2B and Figure 2C As shown in , the polysilicon isl...

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Abstract

An electrostatic discharging protection device contains a semiconductor layer with a source area, a drain area and a channel area which has a grid on it. A number of island shape units scatter sysmmetrically or a symmetrically in the drain area and are made up from polysilicon or isolated oxide.

Description

technical field [0001] The invention relates to an electrostatic discharge (Electrostatic Discharge, ESD) protection device, and in particular to a transistor of an electrostatic discharge protection circuit which can improve efficacy. Background technique [0002] Metal-Oxide-Semiconductor (MOS) integrated circuits receive input signals through the gates of MOS transistors. If a high-voltage input signal is applied to the gate terminal, the gate oxide layer may not be able to withstand this high voltage and cause form a voltage collapse. When semiconductor devices are handled by people or machines, voltages higher than the normal input voltage may be generated. However, abnormally high voltages can come from a number of sources, such as when the surface of an IC is rubbed or an IC is unwrapped from its plastic packaging. Static electricity can range from hundreds of volts to thousands of volts. If such a high voltage is applied to the package lead of an integrated circuit...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02
CPCH01L27/0259H01L2924/0002H01L2924/00
Inventor 林锡聪
Owner WINBOND ELECTRONICS CORP