Multiple enable controller with parallel arbitration mechanism and its method

Abstract

The present invention provides one device and method for distributing system resource in controllers. The controller is provided with one volatile memory, several application circuits and one arbitrator; and each of the application circuits may present one request signal of access to the memory and is set some priority of access to the memory. When several application circuits present request in the same time period, the arbitrator will selects the application circuit with highest priority for access to the memory. The arbitrator includes several arbitration modules corresponding to the application circuits and one general arbitration module to select the application circuit with highest priority from those application circuit selected by the arbitration modules.

Description

Technical field [0001] The present invention provides a device and a related method for arbitrating the access priority of each circuit block to a volatile memory in a controller, in particular, a method for classifying each circuit block into different groups so as to be in different groups. An arbitration device and method capable of shortening arbitration time and simplifying circuit configuration by performing priority arbitration in the group at the same time. Background technique [0002] The controller is one of the most important foundations in modern information construction; the controller can carry out complicated data operations and data management, and has been widely used in various automation devices and computer systems. With the development of technology, the more circuits that can be integrated into the same controller, the more powerful and diverse the functions of the controller. [0003] Generally speaking, there are circuit building bl...

AI Technical Summary

Problems solved by technology

As mentioned above, due to the operation requirements of the controller 10, the arbiter 14 must complete the arbitration of the priority within one clock cycle; Priority arbitration, then the controller 10 cannot operate normally; or the controller 10 must operate with a slower clock

From this point of view, under the requirements of high clock pulse and high operating efficiency of modern controllers, the arbiter 14 of the prior art obviously has difficulties in use.

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