Antinoise and burst mode receiving equipment and method for recovering clock signal and its data

Abstract

A noise-resistive, burst-mode receiving apparatus and a method for recovering a clock signal and data therefrom are provided. The noise-resistive, burst-mode receiving apparatus includes a voltage control signal generator for multiplying frequency of a system clock signal and for generating a voltage control signal whose level corresponds to the multiplied frequency of the system clock signal; a reset signal generator for delaying an input signal which is irregularly input in the unit of packet, in response to the voltage control signal, carrying out an exclusive OR operation on the delayed signal and the input signal, and outputting the result of the exclusive OR operation as a reset signal; a clock signal generator for generating a signal whose level is changed at the middle point of each bit included in the packet, as a recovered clock signal in response to the reset signal and the voltage control signal and for outputting the recovered clock signal; and an output buffer for buffering the input signal and outputting the buffered signal as recovered data in response to the recovered clock signal. According to this apparatus and method, the clock signal and data can be stably recovered even though errors occur in the input signal has errors due to jitter or other factors. Also, an input signal can be locked within 1 bit according to the present invention, and thus, it is possible to speedily recover a clock signal and data.

Description

technical field [0001] The present invention relates to a burst-mode receiving device, and more particularly to a noise-immune, burst-mode receiving device and method for recovering a clock signal and its data. Background technique [0002] Generally, a receiving device of a communication system employs a phase-locked loop (PLL) to recover a clock signal and its data. The PLL can minimize the swing of the edge of the input signal due to jitter or external shock, and thus, can recover the clock signal with the best judged timing in the receiving device. [0003] However, unlike a receiving device employed in a conventional communication system, it is difficult to recover a clock signal and data with a conventional burst mode receiving device using a PLL. This is because the frequency of the input signal input into the receiving device is different from the frequency of the system clock signal used in the burst mode receiving device. In addition, since it is difficult to det...

AI Technical Summary

Problems solved by technology

At this time, since the receiving rate of the input signal is difficult to determine, the conventional burst mode receiving device uses the system clock signal generated from itself

Therefore, if the input signal is continuously fed with 0 or 1, there is a higher possibility that: that is, the number of consecutive bits is misidentified, and there may be a delay of at least 3 bits when the clock signal is restored

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