Semi-conductor storage device

Abstract

A semiconductor memory circuit is disclosed, which comprises a plurality of memory cell blocks, a plurality of sub data lines, a first bank region including the plurality of memory cell blocks and the plurality of sub data lines, at least one of second bank region arranged, a plurality of data read lines, a plurality of first amplifier circuits connected to the plurality of data read lines, a plurality of auto data lines, a plurality of second amplifier circuits connected to the plurality of auto data read lines, a plurality of switch circuits provided in correspondence to the plurality of memory cell blocks, wherein data in the plurality of memory cells of the second bank region are readable from the plurality of first amplifier circuits, even when data in the plurality of memory cells of the first bank region is being read from the plurality of second amplifier circuits.

Description

[0001] Cross reference to related applications [0002] This application is based on and claims priority from prior Japanese Patent Application No. 2001-272072 (filed on September 7, 2001), the contents of which are incorporated herein. technical field [0003] The present invention relates to a nonvolatile semiconductor storage device (EEPROM) capable of electrically erasing / rewriting data, and in particular to a semiconductor having a storage body configured by arranging a plurality of storage elements having a MOS transistor structure in a matrix. Among memory devices, a semiconductor memory having a structure in which other banks can be read while erasing or writing is performed with a certain bank is used for a semiconductor memory (flash memory) capable of collective erasing. Background technique [0004] As a memory cell of an EEPROM, an NMOS transistor having a double stack structure on a double well formed on a semiconductor substrate is known in order to reduce its...

AI Technical Summary

Problems solved by technology

[0038] However, for example, in an 8-word page read level (8-page level) in which 1 word is regarded as 1 page, each data line (SDLj, MDL_Rj, MDL_Aj) is (128+2) respectively, and the occupied area DLA of the data line is It is about 128 μm, which cannot be ignored relative to the chip area, resulting in an increase in the chip area and an increase in manufacturing costs

[0039] As mentioned above, when the existing semiconductor storage device uses double-layer metal wiring to realize the page readout level corresponding to bidirectional operation, there is a problem that the number of data lines is significantly increased, and the chip area of ​​the increased part is increased.

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