Buffer capable of regulating work period and its operation method

A technology of working cycle and buffer, applied in the field of buffer, can solve the problems of abnormal operation of circuit system, inability to increase the speed of circuit system, damage of clock signal quality, etc.

Inactive Publication Date: 2003-04-23
VIA TECH INC
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  • Abstract
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Problems solved by technology

[0008] Therefore, in the known technology, after an ideal clock signal undergoes multiple divergences, the quality of the clock signal will be destroyed to some extent, which may cause the speed of the circuit system to fail to increase, and even cause the entire circuit system to be damaged. abnormal movement

Method used

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  • Buffer capable of regulating work period and its operation method
  • Buffer capable of regulating work period and its operation method
  • Buffer capable of regulating work period and its operation method

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Embodiment Construction

[0037]Because the known buffer will cause problems in the quality of the clock signal, so that the clock signal cannot maintain its duty cycle fixed at 50%, in view of this, the present invention provides a buffer with an adjustable duty cycle and its operation The method is used in the clock path circuit, so that the clock signal input to the clock path circuit can have the same duty cycle as the output clock signal, and the voltage level of the clock signal can be maintained, so that the clock signal can pass through multiple branch paths After that, there is still a certain voltage level to drive the next stage of the circuit. The following description is an embodiment of the present invention, basically, this kind of buffer used for adjustable duty cycle is composed of two such as Figure 5 The programmable inverter shown in the series is composed of, please refer to Figure 5 , the circuit is composed of PFET group 500 , PFET group 502 , NFET group 510 , NFET group 512 a...

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Abstract

The present invention relates to a buffer capable of regulating working period and its operation method. Said method is used for applying it to series-connected inverters. Every inverter possesses several charging current pathways and several discharging current pathways, when the working period of clock signal is reduced, the number of discharging current pathways is reduced and the number of charging current pathways is reduced. Said invention uses the buffer on the clock pathway circuit for providing adjustable working period to dynamically regulate the time of rising edge and falling edgeof clock signal so as to dynamically change working period of clock signal.

Description

technical field [0001] The present invention relates to a buffer and its operating method, and in particular to a buffer used in a clock path circuit to control the duty cycle of a clock signal and its operating method. Background technique [0002] Generally speaking, in the current integrated circuit design system, one or even multiple clock signals (Clock Signal) with different frequencies are required, and the action timing and working speed of the integrated circuit system all depend on the clock signal on the integrated circuit system. The clock signal is used as a reference. When the frequency of the clock signal on the circuit system is faster, the working speed of the circuit system is usually relatively faster. Therefore, the quality of the clock signal is very important for the circuit system. If the circuit system If the quality of the clock signal is not paid special attention and handled carefully, it may cause the speed of the circuit system to fail to increas...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/00H03K5/01H03K19/0185H03K19/20
Inventor 张棋
Owner VIA TECH INC
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