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Method for making memroy element

A technology for memory components and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., and can solve problems such as damage to the oxide layer and incomplete etching

Inactive Publication Date: 2003-08-06
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this method uses one etching process to simultaneously pattern the conductive layer and the strip-shaped polysilicon layer. Therefore, due to the problem of high aspect ratio (High Aspect Ratio), it is easy to cause incomplete etching.
In addition, due to the etching process parameters used to form polysilicon islands in known methods, the oxide layer and even the substrate surface are often damaged.

Method used

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  • Method for making memroy element
  • Method for making memroy element
  • Method for making memroy element

Examples

Experimental program
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Embodiment Construction

[0029] Figure 2A to Figure 2P , which is a method for manufacturing a memory element according to a preferred embodiment of the present invention.

[0030] Please refer to Figure 2A First, a thin dielectric layer 202 , a polysilicon layer 204 , a capping layer 206 and a patterned photoresist layer 208 are sequentially formed on the provided substrate 200 . Wherein, the thin dielectric layer 202 is a tunnel oxide layer for flash memory, and a gate oxide layer for mask read only memory. The material of the cap layer 206 is, for example, silicon nitride.

[0031] After that, please refer to Figure 2B , using the photoresist layer 208 as an etching mask to pattern the top cover layer 206 and the polysilicon layer 204 to form a strip-shaped conductive structure 205 . Next, a buried bit line 201 is formed in the substrate 200 on both sides of the elongated conductive structure 205 by ion implantation.

[0032] Then, please refer to Figure 2C , depositing a bottom anti-refl...

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Abstract

A process method for memory element is to form a thin dielectric layer on a provided base and form a strip conductive structure composed of a polysilicon layer and a top-cover layer on the thin dielectric layer then to form a built-in position lead on the base both sides of the conducting structure and a bottom anti-reflection layer above the base, then, further to form several polysilicon islands with patternized bottom anti-reflection layer vertical to the strip conducting structure and the said structure to form a figure line on the islands.

Description

technical field [0001] The present invention relates to a method for manufacturing a memory element, and in particular to a method for manufacturing a polysilicon island (Poly-Island) of the memory element. Background technique [0002] Memory, as the name implies, is a semiconductor device used to store data or data. In the storage of digital data, we usually use bits (Bit) to form the capacity of the memory. Each unit used to store data in the memory is called a storage unit (Cell). The specific location of the storage unit among the tens of thousands of storage bits is called an address. In other words, the memory cells are arranged in an array in the memory, and each combination of row and column represents a specific memory cell address. Wherein, several memory cells listed in the same line or in the same column are connected in series by a common wire. The wire connecting the memory cells is called a word line, and another wire perpendicular to the word line is cal...

Claims

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Application Information

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IPC IPC(8): H01L21/8239
Inventor 余旭升李俊鸿
Owner MACRONIX INT CO LTD