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Semiconductor integrated circuit device

A technology of integrated circuits and semiconductors, which is applied in the manufacture of semiconductor devices, circuits, semiconductor/solid-state devices, etc., and can solve problems such as uneven application of ESD loads to transistors and transistor damage

Inactive Publication Date: 2004-03-17
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is, the signal line 3 has a parasitic resistance, so the ESD load is unevenly applied to the transistors of the protection circuit
Therefore, any transistor with the greatest ESD load applied will be destroyed

Method used

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  • Semiconductor integrated circuit device
  • Semiconductor integrated circuit device
  • Semiconductor integrated circuit device

Examples

Experimental program
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Effect test

Embodiment Construction

[0022] Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Figure 4 A circuit diagram showing a partial configuration of a protection circuit in the semiconductor integrated circuit device according to the first embodiment of the present invention. Figure 4 Only a portion is shown, namely: with image 3 The conventional configuration shown corresponds to the n-channel transistor region, and although not particularly shown, the overall configuration of the circuit according to the first embodiment is the same as figure 1 The conventional circuit shown is similar. Therefore, descriptions of these parts will be omitted in order to avoid redundant descriptions.

[0024] Such as Figure 4 As shown, in n-channel transistor region 28, resistor 25a of region A has resistance RA, and resistor 25b of region B has resistance RB. The resistance RA is larger than the resistance RB by a value correspon...

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PUM

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Abstract

In a semiconductor integrated circuit device, an n-channel transistor area has an area A on a pad side and an area B on an internal circuit side, where a plurality of protective elements are connected in parallel between a signal line and a power supply line. Each of the protective elements has resistors. Resistance of the resistors in the area A is set higher than resistance of the resistors in the area B by a value corresponding to resistance of parasitic resistance of the signal line included in the area A so that the resistance of the protective elements in the areas A and B are the same or almost the same as each other. A p-channel transistor area has the same configuration as that of the n-channel transistor area.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit device provided with a protection element for protecting a metal oxide semiconductor (MOS) transistor from electrostatic damage. Background technique [0002] Generally, an integrated circuit formed by using a complementary metal-oxide-semiconductor (CMOS) integrated circuit is provided with a protection element for protecting input / output (I / O) circuits from electrostatic damage. Therefore, when forming a protection element using a MOS transistor, it is necessary to prevent the protection element from being destroyed by static electricity. [0003] Conventionally, as an I / O circuit of a semiconductor integrated circuit, a narrow pitch I / O circuit is known. A narrow-pitch I / O circuit can be obtained by arranging a plurality of transistors in the I / O circuit in advance and changing the layout of wiring for connecting the transistors as necessary. By changing this layout, I / O circuits ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/04G11C7/24H01L21/822H01L21/8238H01L23/60H01L23/62H01L27/00H01L27/02H01L27/06H01L27/092
CPCH01L27/0266G11C7/24
Inventor 斋藤则章相泽克明木谷和弘
Owner FUJITSU LTD